Multimedia Core IP RTL Design Engineer

You should have a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture, or equivalent practical experience. With 4 years of experience in RTL coding and experience with RTL quality checks methodologies such as Lint, CDC, RDC. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a specialization in computer architecture is preferred. Experience in implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs like Display or Video Codecs would be advantageous. Also, familiarity with ASIC design methodologies for clock domain checks and reset checks is preferred. Join a team that pioneers innovation, crafting custom silicon solutions to drive the future of Google's direct-to-consumer products. Contribute to developing products that are adored by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. The gChips team focuses on custom silicon solutions that enhance user experiences in Google Hardware products, optimizing performance and power for specific use cases. This includes SoCs and other integrated circuits for the product portfolio. Collaborating with various teams across Google, gChips identifies silicon requirements for the future and stays informed about the latest chip technologies and standards. As part of the team designing interconnect IP for Pixel SoCs, you will work with architecture, software, verification, power, timing, and synthesis teams to deliver quality RTL. Your responsibilities will include developing microarchitecture, Verilog/SystemVerilog RTL coding, simulation debugging, and RTL implementations meeting power, performance, and area goals. You will also be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up, along with collaborating with global teams at different sites. Google's mission is to make the world's information universally accessible and useful, combining AI, Software, and Hardware expertise to create innovative experiences. By researching, designing, and developing new technologies, we aim to enhance computing speed, seamlessness, and power, ultimately improving people's lives through technology. Your responsibilities will involve collaborating with architects to develop microarchitecture, RTL coding, and performing simulation, debug, and quality checks. You will work on RTL implementations meeting power, performance, and area goals, participate in synthesis and timing/power closure, and support pre-silicon and post-silicon activities. Additionally, you will travel to collaborate with global teams at different sites worldwide.,