2736 Verilog Jobs - Page 9

🚀 Immediate Hiring – Design Verification Engineer (Pre-Silicon DV) 📍 Location: Pune / Bangalore / WFH (Hybrid Mode) 📅 Experience: 7+ Years 🎓 Qualification: MS (or higher) in EE / EC / ECC Engineering We are looking for an experienced and self-driven Design Verification Engineer to join the NXP WCS/SCE BU team. If you’re passionate about Pre-Silicon Verification and ready to contribute to cutting-edge IPs & SoCs, we want you onboard immediately ! Key Responsibilities Develop SystemVerilog based UVM/OVM testbenches for IP & SoC verification. Work on Low Power Simulation setups, UPF flows, debug power-related simulation failures. Create assertion checkers , coverage monitors , and develop assembly/C-based diagnostics . Analyze coverage data , debug simulation failures, and refine verification plans . Collaborate closely with design and architecture teams for end-to-end verification. Must-Have Skills ✅ Strong expertise in Verilog & SystemVerilog (Assertions, Testbench Methodologies) ✅ UVM / OVM Methodology – Complex testbench development ✅ AMBA Protocols (AXI, AHB, APB), PCIe MAC, USB MAC, Bluetooth MAC, Wi-Fi 802.11 MAC ✅ Low Power Verification – UPF setup, debug ✅ Scripting Skills – Perl, Unix Shell, or equivalent ✅ Solid Computer Architecture Knowledge ✅ Excellent debugging skills & problem-solving mindset Good to Have Assembly language programming knowledge Why Join Us? Work on world-class semiconductor designs . Flexible Hybrid / WFH options. Immediate joining opportunity. 📩 Apply Now – Send your updated CV to prabhu.p@acldigital.com or Whatsapp +91 87543 87484 with the subject line:

Eteros Technologies is looking for experienced ASIC Verification Design Engineers to join our team Looking only for Immediate joiners. We are seeking individuals with 5 to 15 years of experience to be a part of our projects, working on innovative cutting-edge technologies. Work Location: Bangalore/ Hyderabad/ Ahmedabad Experience from 5 yrs to 15 years in SoC level Verification Looking only for Immediate joiners. Proficiency in System Verilog and UVM Exposure to verifying DSP based SoC designs(with Smart Cache/TCM and Familiar with Multiply and accumulate unit ( MAC) Experience with SoC memory sub-system, LPDDR. Writing C code and working on System Verilog-C (SV-C) testbenches. Must be familiar with ARM/RISC-V subsystems. Familiar with one or more protocols like AMBA protocols, JTAG, SPI, Ethernet, UCIE etc Eteros Technologies, Inc. is a Semiconductor Engineering services startup, Founded in 2020 in Silicon Valley and led by professionals with over 150 years of combined semiconductor design experience, the Eteros team has numerous successful tape outs under its belt and a global presence of customers spanning the US, Europe and APAC. We work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Kindly visit (https://www.eterostech.com/) for more details.

As an experienced FPGA Design Engineer in the field of wireless communication, you will be joining the core R&D team of our client, a leading company specializing in optical wireless communication (OWC) and LiFi technology. Your primary responsibility will be to work on high-speed wireless communication systems, starting from the conceptualization phase all the way to integration. Your key responsibilities will include FPGA design and development utilizing VHDL, Verilog, or SystemVerilog. You will focus on implementing high-speed digital designs with an emphasis on modulation/demodulation techniques such as QPSK, QAM, and OFDM. Additionally, you will lead technical project teams to ensure timely delivery within budget constraints. Developing communication system architectures for wireless networks and staying abreast of FPGA advancements and multi-core microprocessor platforms will also be part of your role. To excel in this position, you are required to hold a Master's or PhD in FPGA/RTL Design or a related field, along with a minimum of 5 years of experience in FPGA design, particularly in wireless communication domains like 3G, 4G, WiFi, and WiMax. Strong verification skills for high-speed design implementation, a solid understanding of networking protocols, and wireless communication concepts are essential. Your analytical, problem-solving, and teamwork skills will also be critical to your success in this role. This opportunity offers you the chance to work on cutting-edge LiFi technology with global deployment potential. You will be part of an innovative and fast-growing R&D environment that provides opportunities for rapid career advancement based on your performance.,

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. You have the opportunity to join the Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, two industry leaders have united to create an optical networking powerhouse, combining cutting-edge technology with proven leadership to redefine the future of connectivity. As an FPGA Verification engineer, you will play a crucial role in designing verification plans, developing environment/testbenches, creating test scenarios for running simulations, conducting coverage analysis, and providing lab support during board bring up to ensure the quality of Infinera products. You should possess the ability to handle projects independently and demonstrate a strong drive for finding solutions. Your responsibilities will include developing and executing verification plans for high-complexity DWDM systems used in LH/ULH optical network applications, designing and implementing simulation environments and testbenches, running test scenarios to ensure comprehensive design coverage, performing coverage analysis, collaborating with cross-functional R&D teams, providing lab support during board bring-up, and managing verification projects independently with a proactive approach. Key skills and experience required for this role include 12-16 years of experience in developing System Verilog UVM based test environments, HVL coding skills for Verification, familiarity with UVM verification methodologies, knowledge of HDLs such as Verilog and scripting languages like perl, conversance with technologies like Ethernet, PCIe, I2C, SPI, structured analytical and troubleshooting skills, good communication skills, and a self-driven and innovative mindset. Nokia is committed to innovation and technology leadership across mobile, fixed, and cloud networks. Joining Nokia will provide continuous learning opportunities, well-being programs, opportunities to join employee resource groups, mentoring programs, and the chance to work in highly diverse teams with an inclusive culture. Nokia is an equal opportunity employer committed to creating a culture of inclusion where everyone feels respected, included, and empowered to succeed.,

You will be responsible for the Tools and Infrastructure Platforms for the engineering team at Ethernovia. This responsibility includes developing software for Ethernovia's Evaluation platforms that are used to debug, test, and demonstrate the company's networking devices. This software includes BSP (Board Support Packages), drivers for onboard devices, middleware software. Our products and hence tool infrastructure is quite data intensive and we are looking for candidates who are able to create tools for handling large volume of test data output and help visualize this data in command line and graphic tools. Technical Qualifications Bachelors or Master's degree in Computer Science/Software or related field. Work Experience: 3 years for Mid-level and 7 years for Senior Level position. Strong understanding of Software Development lifecycle including Architecture, Implementation and Testing fundamentals. Proficient in C/C++ Programming Language. Experience in Python is a plus. Experience with BSP (Board Support Packages) preferably Linux systems like Beaglebone or Raspberry Pi. Device drivers, preferably for devices on hardware buses like I2C, SPI and Ethernet. Good understanding of Operating systems preferably Embedded Linux. Experience with integration and testing of open-source middleware, libraries, and drivers. Hands on Experience with Hardware and embedded processors. Nice to Have Experience with GNU or similar compiler, debugging suite. Embedded programming, preferably with communication devices and hardware buses like I2C, SPI, Ethernet, USB. Code Version Control and Review tools/processes like Perforce/Git, Swarm. Automation and DevOps tools like Jenkins. ARM family of processors or similar embedded processors. Performance testing of communication devices. GRPC, Protobuf or similar Remote Procedure Call (RPC) software. Boot code like uboot or similar. Experience in Verification/validation experience including HW languages (System Verilog, Verilog, UVM) is a big plus. Experience in SystemC and transaction-level modelling (TLM). Soft Skills Self-motivated and able to work effectively both independently and in a team. Excellent communication/documentation skills. Attention to details. What you'll get in return: Pre IPO stock options Cutting edge technology World class team Competitive base salary Flexible hours Medical, dental and vision insurance for employees Flexible vacation time to promote a healthy work-life balance,

As a FPGA & Board Design Engineer with 2 to 5 years of experience, you will be responsible for developing new hardware designs. This includes system design, CPLD/FPGA or processor design, and board-level analog/digital circuit design for embedded systems/boards. Your primary task will be to create detailed specifications based on requirements and implement hardware designs accordingly. You will work closely with the CAD team for layout review and feedback, perform simulation activities, and develop test benches to complete the verification of FPGA designs. Additionally, you will be involved in proto H/W bring-up with support from firmware engineers. To qualify for this role, you should hold a B.Tech. or M.Tech. in EE with at least 2+ years of FPGA experience, including implementation, synthesis, and timing closure. Proficiency in Verilog, VHDL, and System Verilog is required, along with experience in tools such as Synopsys Synplify, Xilinx Vivado, and ISE. Hands-on experience with FPGA debug methodologies, schematic capture tools, lab debug equipment, and scripting skills in Perl/Python are essential. Knowledge of high-speed interfaces like PCIe, Ethernet, and DDR3/4, as well as low-speed interfaces including SPI, IIC, and UART, is expected. Experience in test bench design and implementation, designing with Altera and Xilinx FPGAs, and strong attention to detail are also necessary. Good interpersonal skills and excellent written and verbal communication skills are a bonus for this role.,

We are looking for an experienced Staff Design Engineer CPU RTL to take on the responsibility of leading and owning RTL development for one or more modules of a high-performance CPU core. Your role will encompass all facets of the design, including Performance, Power, and Area. In this position, you will be expected to drive the micro-architecture and design of a critical CPU block or multiple blocks of a CPU core. You will work closely with the CPU modeling team to explore high-performance strategies. Your responsibilities will also include developing microarchitecture and specifications, configuring design features, and refining RTL design to meet power, performance, area, and timing objectives. Additionally, you will provide support for functional verification and assist in defining the design verification strategy. Collaborating with a multi-functional engineering team, you will help implement and validate physical design aspects related to timing, area, reliability, testability, and power. To qualify for this role, you must have hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core. A thorough understanding of microprocessor architecture is essential, particularly in areas such as Instruction fetch and decode, branch prediction, Instruction scheduling, register renaming, Out-of-order execution, Integer and Floating-point execution, Load, Store execution, prefetching, Cache, and memory subsystems. Proficiency in Verilog and/or VHDL, experience with simulators and waveform debugging tools, and knowledge of logic design principles are required. Ideally, you should hold a Masters degree with 5-8 years of experience or a PhD with 3-4 years of work experience. Candidates with experience in designing RISC-V, ARM, and/or MIPS CPUs, hardware multi-threading, virtualization, and SIMD designs will be given bonus points. Familiarity with high-performance and low-power microarchitecture techniques, as well as expertise in using scripting languages like Perl or Python, is advantageous. At MIPS, you will be joining a dynamic team of technologists dedicated to developing the industry's highest performance RISC-V processors. You will have the opportunity to work in small teams within a non-compartmentalized structure, offering autonomy and the chance to contribute to the bigger picture. With support from experienced CPU engineers, you can chart your own growth path within the organization. Additionally, you will gain valuable insights into the RISC-V architecture and its applications by working with industry-leading customers. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave for employees and their families. MIPS is recognized as a pioneer in microprocessor technology, with a legacy of leading RISC-based computing for various applications. Building on over 30 years of expertise, MIPS is at the forefront of the RISC-V revolution, focusing on developing high-performance processors like the MIPS eVocore series. As a part of the MIPS team, you will play a key role in accelerating the adoption of RISC-V solutions with cutting-edge technologies and deep engineering knowledge.,

As a highly skilled R&D Staff Engineer at Synopsys, you will be at the forefront of designing and developing state-of-the-art EDA tools with innovative algorithms for static low power verification products. With your expertise in C/C++, data structures, and algorithms, you will collaborate with local and remote teams to ensure seamless integration and execution. Your background in Electronic Design Automation (EDA) tools and methodologies, along with your proficiency in Verilog, SystemVerilog, and VHDL, will position you as a leader in the field. Your responsibilities will include working directly with customers to understand their requirements, providing online debugging, and tracking delivery and execution. You will lead a small team, guiding them through technical challenges and project milestones, while contributing to the continuous improvement of the static low power verification product. Additionally, you will explore new architectures and lead the development of cutting-edge solutions. Your impact will be significant as you drive the development of advanced EDA tools, enhance the quality and reliability of the static low power verification product, and provide critical support to customers. By leading and mentoring junior engineers, you will foster a culture of innovation and excellence within the team, contributing to Synopsys" reputation as a leader in the semiconductor and EDA industries. Your role will be pivotal in the successful execution of projects, meeting deadlines, and exceeding expectations. To excel in this role, you will need fluency in C/C++, a strong background in data structures and algorithms, experience with UPF, familiarity with Tcl and Python-based development on Unix, and knowledge of Verilog, SystemVerilog, and VHDL HDL. Your ability to develop new architectures and demonstrate strong leadership skills will be crucial to your success. As a dynamic and innovative engineer with a passion for technology and a commitment to quality, you will play a key role in a collaborative and productive work environment. Your problem-solving skills, critical thinking ability, and self-motivation will be assets that drive your success in this role. By being detail-oriented and setting high standards for quality and reliability, you will make valuable contributions to the team. You will be part of the Static Verification team at Synopsys, working alongside talented engineers dedicated to developing and enhancing static low power verification products. This team collaborates closely with other departments to ensure seamless integration and execution, contributing to the success of Synopsys and its customers. Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process. Join us at Synopsys to transform the future through continuous technological innovation.,

As the Lead Verification Engineer at a cutting-edge storage startup in Silicon Valley, you will be responsible for tackling IP and SoC level verification challenges within a Multi-core, complex, high-performance ASIC environment. Your role will involve understanding internal requirements and complexities of the SOC, designing verification methodologies, environments, and test plans, and collaborating with the design team to ensure high-quality verification for first-pass success of the SoC. Located in Bangalore, KA, India, you should hold a BA/BS degree in Electrical/Electronics Engineering with over 10 years of practical experience. Strong fundamentals in digital ASIC design and verification, expertise in ARM cores and related infrastructure, familiarity with AMBA bus protocols, and experience with Verilog, SystemVerilog, UVM, and other verification tools are essential. Knowledge of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, and UART is desirable, along with an understanding of IP designs and verification requirements. Your responsibilities will include defining and developing verification methodologies and test plans based on functional coverage, project management, contributing to IP and SoC verification, collaborating with the design team for design quality improvement, mentoring team members, and establishing processes for verification and quality improvements. Additionally, you will be involved in Gate Level Simulations (GLS), emulation, FPGA-based, and Post Si validation. To excel in this role, you must possess excellent communication and leadership skills to lead a team of verification engineers effectively. Your ability to review test plans, verification tests, and coverage for team members, as well as your strong test creation, debugging capabilities, and functional coverage understanding, will be critical for the success of the projects.,

Selected Intern’s Day-to-day Responsibilities Include Working on various electronics projects and ensuring timely completion Applying knowledge or demonstrating interest in fields such as embedded systems, Internet of Things (IoT), robotics, FPGA, Verilog, PCB designing, and artificial intelligence/machine learning (AI/ML) Being available to work from the office as required Criteria - The applicant can work from Home only if he/she can purchase the project materials by themselves; otherwise, they have to work from the office. Candidates from any location other than Silvassa may apply, but only if they are willing to purchase the components on their own Note : The cost of components/project materials will be reimbursed after the successful delivery of the correct project. Stipend - INR 2000 per month Internship Duration - 2 to 6 months

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFX - SMTS SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. The Person A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Key Responsiblities Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. Preferred Experience Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience in design and development of Security or Audio blocks. Experience with a scripting language like Perl or Python. Experience with DSI2 or MIPI C/D Phy. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Collaborate with architects and develop microarchitecture. Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks. Participate in test planning and coverage analysis. Develop RTL implementations that meet engaged power, performance and area goals. Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up. Create tools/scripts to automate tasks and track progress. Work with multi-disciplined and multi-site teams in Architecture, RTL design, verification, DFT and Partner Domains. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

7+ experience in verification with strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI Solid understanding of digital hardware design and Verilog HDL. Detailed understanding and experience of the current verification strategies required for sophisticated SoC development, including software-based techniques Good knowledge of test plan creation and tracking Experience with Perl, Python or other scripting language

Key Responsibilities: Design and develop RTL for ASIC/FPGA systems using Verilog and VHDL Define and implement Micro-Architecture specifications based on system-level requirements Perform RTL Integration, Synthesis, Linting, and STA (Static Timing Analysis) Execute CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and LEC (Logical Equivalence Check) Collaborate with architecture, verification, and backend teams throughout the design cycle Automate design and verification flows using scripting Must have Experience: Minimum 5+, ideally 7+ years of experience with any 2 or 3 of the following is must: “SoC” OR “System-on-a-Chip” “PCIe” OR “PCI-E” CPU OR processor OR RISC Required Skills: Strong understanding of Digital Design and Micro-Architecture Development RTL coding expertise in Verilog and VHDL Basic knowledge of SystemVerilog Hands-on experience with Lint, Synthesis, LEC, CDC, RDC, STA, and RTL Integration Experience working in Linux environments Scripting skills in TCL, Python, Perl, or Shell

Qualcomm India Private Limited is looking for a skilled individual to join their Engineering Group, specifically focusing on Hardware Engineering. As a member of Qualcomm, you will be part of a team of inventors who have paved the way for 5G technology, leading to a new era of connectivity and endless possibilities that will revolutionize industries, generate employment opportunities, and improve lives. This is just the beginning of the Invention Age, and your expertise is crucial in turning 5G's potential into groundbreaking technologies and products. At Qualcomm CDMA Technologies (QCT), a prominent player in Multimedia integrated circuits, software, and systems for wireless consumer devices, including Smartphones, Netbooks, and E-readers, you will be involved in developing cutting-edge technologies to enhance mobile devices across various domains such as 2D and 3D graphics, audio/video, display, and architecture. Your role will encompass the design and implementation of leading-edge graphics processors, focusing on areas like 2D and 3D graphics, streaming processors, high-speed IO interfaces, and bus protocols. You will be responsible for the architecture and micro-architecture design of the ASIC, RTL design and synthesis, as well as logic and timing verification. The successful candidate will work on specifying and designing digital blocks in the Multimedia Graphics team to be integrated into a wide range of devices. Collaboration and active support for diversity within the team and the company are expected from all Qualcomm employees. **Minimum Qualifications:** - Bachelor's degree in Science, Engineering, or a related field - Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume production - Experience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and design-for-test (DFT) - Knowledge of Computer Architecture, Computer Arithmetic, C/C++ programming languages is desired - Exposure to DX9~12 level graphics HW development is an advantage - Strong communication skills and a collaborative mindset - Required: Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field. - Preferred: Master's degree in Computer Science, Electrical Engineering, Information Systems, or related field. **Additional Requirements:** - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 6+ years of Hardware Engineering or related work experience - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 5+ years of Hardware Engineering or related work experience - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of Hardware Engineering or related work experience Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities throughout the hiring process. Employees are expected to adhere to all applicable policies and procedures, including those related to confidentiality and security protocols. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. This job posting is intended for individuals seeking direct employment with Qualcomm. For more information about this role, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation teams for pre/post Silicon debug is expected, and hands-on experience in Low power design is preferable. Additionally, experience in Synthesis and understanding of timing concepts for ASIC is essential. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in the relevant fields with 2+ years of experience or a PhD with 1+ year of experience would also be considered. Qualcomm is an equal opportunity employer committed to providing accessibility to individuals with disabilities throughout the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not bear responsibility for any fees related to such submissions. For more information about this role, please contact Qualcomm Careers.,

This is a full-time role for a Senior Design Verification Engineer for Brainchip’s Hyderabad, India Office. This role is responsible for performing functional verification. Key tasks include debugging, ensuring designs meet customer requirements, documenting verification plans, and collaborating with cross-functional teams to improve the verification process. Responsibilities Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies. Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Perform functional coverage driven verification closure. Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Qualifications B.Tech/M.Tech. with 5-10 years of relevant experience. Experience in verification of complex IPs/units and sub-systems. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies. Expertise in Verilog. Knowledge in System Verilog or similar hardware verification language. Familiarity with verification methodologies like UVM and exposure to industry standard verification tools for simulation and debug. Experience with System Verilog Assertion (SVA) a plus. Experience with Perl, Python or other scripting language is a plus Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus

As a skilled and experienced Digital Circuit Design Engineer, your primary responsibility will be leading the design, development, and validation of high-performance digital systems. You should have expertise in digital logic design, proficiency with HDL languages and FPGA tools, and a strong grasp of embedded systems integration. Your key responsibilities will include designing and implementing complex digital circuits such as logic gates, finite state machines, and synchronous/asynchronous architectures. You will utilize industry-standard tools like Verilog, VHDL, and FPGA development environments for simulation, synthesis, and verification. Additionally, integrating digital designs with communication and memory protocols like PCIe, DDR, UART, USB, and SPI will be crucial. In this role, you will be expected to conduct thorough testing, debugging, and optimization of digital systems. Collaboration with firmware and embedded software teams using C/C++ or Python for system-level integration will also be a significant part of your job. To qualify for this position, you should hold a B.Tech/M.Tech degree in ECE/Embedded Systems/Digital Electronics and possess a minimum of 3 years of relevant experience.,

Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. If you flourish in a fast-paced, results-oriented environment, want to achieve individual success within a team-first organization, and believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Lattice Semiconductor is seeking a development test engineer to join the EDA tools development team in Pune. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, and grow. As a development test engineer at Lattice, you will work closely with the EDA tools development team to understand new features and develop validation plans for those features in Verilog or HDL. You will implement and maintain tests for the EDA tools covering both back-end and the GUI modules using Squish or QtTest. Participation in Agile scrum process to support a high productivity and high impact EDA tools team will be expected. Additionally, you will lead test automation efforts to convert all manual test cases into fully automated test-suites for our development tests and assist with special projects and other duties as assigned. The ideal candidate for this role will have a bachelor's or master's degree in computer science, electronics/electrical engineering, or equivalent. Strong technical development testing skills in the context of C++ development are required. Additionally, very good knowledge and experience in automation and scripting with familiarity in TCl/Tk and Python are essential. Strong written and verbal communication skills, including the ability to effectively communicate technical issues to individuals at all levels of a global organization, will be beneficial. The ability to work in a fast-paced environment, prioritize appropriately, and manage competing priorities is a key attribute for success in this role. Lattice Semiconductor recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. A comprehensive compensation and benefits program is provided to attract, retain, motivate, reward, and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low-cost, low-power programmable design solutions. The global workforce, approximately 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how Lattice's FPGA, CPLD, and programmable power management devices help customers unlock their innovation, visit www.latticesemi.com. Lattice values the diversity of individuals, ideas, perspectives, insights, and values that employees bring to the workplace. Applications are welcome from all qualified candidates. Feel the energy with Lattice.,

About Us ACL Digital is a design-led Digital Experience, Product Innovation, Solutions, and Consulting offerings leader. From strategy to design, implementation, and management, we help accelerate innovation and transform businesses. Keeping customer journeys and design at the core, it is committed to enabling large Enterprises, SMBs, and start-ups to transform. A pioneer in delivering Business Innovation, Integration, and Transformation through disruptive technologies, ACL Digital brings in competitive advantage, innovation, and fresh perspectives to business challenges. With a multi-cultural and transnational talent and as part of the ALTEN Group comprising over 37,000 employees spread across more than 25 countries, it promotes a collaborative knowledge-building environment. Roles and Responsibility PFB the JD. JD Lead: 1 or 2 or 3 based on the options we get 15 years of experience in Design Verification Strong experience in Processor based SoC verification Strong experience in ARM Cortex M or A series designs. Must have worked on bringing up the boot code, writing ISR, exceptions and other functions Strong experience in System Verilog and UVM based design verification Experience in Tensilica xtensa designs is a big plus Must have lead at least 2 to 3 SoC DV or Processor subsystem projects with a team size of 10 Engineers Must have strong experience in AMBA protocols Must have strong understanding of the functioning of Cache controllers, DMA & memory management controllers/ techniques JD Engineer: 9 members 3 to 10 years of experience in Design Verification Good experience in Processor based SoC Verification is a must Experience in writing C or Assembly test cases is a must Strong experience in AHB or AXI protocol is a must System Verilog and UVM experience is a must JD Engineer: 6 members 3 to 10 years of experience in Design Verification Good experience in Processor based SoC Verification is a must OR strong experience in IP verification using SV/ UVM is a must Experience in writing C or Assembly test cases is a plus Strong experience in AHB or AXI protocol is a must Location: Pune or Noida or Bangalore Each location needs a lead team of 3 to 4 to a minimum If we can set it up in one location that would be great

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job Description We are seeking a highly skilled and experienced Principal Engineer in Logic Verification to join our innovative team in Bengaluru, India. As a Principal Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC Create verification environment using UVM methodology Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions Development of tools for Design and Verification support Debug failures and root-cause it by interacting with other teams/groups Etc. Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic - Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable - Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations Proficiency in Verilog, System Verilog & Assertions Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Able to mentor junior members and work with global cross functional team Exposure to Analog verification will additional plus point Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) (SRAM/DRAM/ROM/Flash) Circuits/Logic Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jasper, VS Formal Cadence Schematic and layout environment Qualifications Bachelor's or Master's degree in Computer Science or a related field B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering 8 to 14 years of front end verification experience, with a proven track record of leading complex technical projects Expert-level proficiency in UVM Strong experience with end to end verification including test bench creation, test plan creation, test case development, SVA development and formal verification Proficiency in Functional Coverage definition, regression and debug to close verification deliverables with 100% coverage Ability to work effectively in a fast-paced, agile environment Strong analytical and detail-oriented approach Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

JD Design Verification • Understanding the business requirements and functional specifications of the IPs, subsystems and SOC • Creating Verification Environment Architecture document • Reviewing and Revising: working towards meeting agreed upon acceptance criteria • Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification • Performing RTL simulations using Synopsys and Cadence simulators • Debugging and resolving problems found by simulations .Performance test plan development and maintenance • Development of transactors, monitors and models for performance verification. • Implement performance verification flow including monitoring, synchronization, reporting and self-checking mechanisms • Provide full report of performance metrics and bottlenecks • Tracking tickets and code releases using Bug Tracking tool and GIT • Performing UPF (Unified Power Format) based Power Aware simulations • Coding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions) • Code & Functional Coverage Closure Performing Gate Level simulations .Preparing and conducting reviews of Verification Sign-off documents to ensure SOC tape-out quality

Greetings from 3GHR Services!! We are Hiring for "PCB Designer" position Role: PCB Designer (Printed Circuits Board) Qualification: Btech (ECE / EEE) Experience – 3+ Years Salary – up to 9 LPA (negotiable) Location – Hyderabad Job Overview The company seeking a highly skilled Senior PCB Designer with expertise in FPGA-based designs and Digital Signal Processing (DSP). The ideal candidate will be responsible for schematic design, PCB layout, signal integrity analysis, and simulation for high-performance electronic systems, with a particular focus on high-speed FPGA systems and DSP boards requiring meticulous signal integrity considerations. The candidate will lead the PCB design process, ensuring compliance with IPC 2221, IEC, and other relevant industry standards. They will collaborate with hardware engineers, firmware developers, and manufacturing teams to develop optimized circuit boards. Juniors will be provided for assistance in schematic capture, PCB layout, and documentation. Key Responsibilities PCB Design: Design and develop complex FPGA-based and DSP-based PCB layouts for new products or modifications based on engineering requirements and constraints. Component Selection: Work closely with hardware engineers to select appropriate components that meet electrical, mechanical, and signal integrity requirements. Schematic Capture: Create and maintain schematic diagrams for FPGA and DSP applications using industry-standard EDA (Electronic Design Automation) tools. Design Optimization: Optimize PCB designs for signal integrity, power integrity, performance, cost, manufacturability, and reliability. Design Verification: Perform design validation, signal integrity testing, and simulation to ensure adherence to specifications and industry standards. Collaboration: Coordinate with mechanical engineers, FPGA designers, firmware developers, and manufacturing teams to ensure seamless integration and production readiness. Documentation: Prepare and maintain comprehensive design documentation including PCB specifications, design files, signal integrity analysis reports, and bills of materials (BOMs). Prototyping Support: Support prototype builds and debugging efforts, and iterate designs based on test results and feedback Experience: Proven experience (3+ years) in PCB design with a strong emphasis on FPGA board development and Digital Signal Processing applications. Experience with multilayer PCB design, high-speed digital, and mixed-signal circuits . Skills: Strong proficiency in using PCB design software such as Cadence Allegro, Altium Designer, or equivalent tools. Deep understanding of high-speed signal routing, impedance control, power distribution networks (PDN), and signal integrity analysis. Strong knowledge of PCB layout principles for FPGA, DSP, and high-speed systems, including EMC/EMI mitigation techniques. Familiarity with industry standards like IPC 2221, IPC-7351, IEC standards. Expertise in Design for Manufacturing (DFM) and Design for Assembly (DFA) principles. Communication: Excellent verbal and written communication skills, with the ability to collaborate effectively across interdisciplinary teams. Attention to Detail: Meticulous attention to detail and a commitment to producing high-quality, reliable, and robust PCB designs. Preferred Skills (Bonus Points!) Hands-on experience in signal integrity simulation tools (e.g., Hyper Lynx, Sigrity, ANSYS SIwave). Familiarity with FPGA programming (VHDL/Verilog) for better design integration. Experience with 3D PCB modelling and thermal analysis. Background in RF and high-frequency PCB layout is a plus. Job Type: Full-time Pay: ₹700,000.00 - ₹900,000.00 per year Work Location: In person

Boltchip is a Singapore based Transformation Consulting company setting up Global Capability centres for global clients in ASIA. We are on the lookout for a team of Senior Design Verification engineers for our client in India. Location – India (Bangalore & Ahmedabad ( Onsite only )) Qualification (s) – BE/ BTech/ MTech/MS/ PhD Domain - Electronics, Electrical, Computer Engineering or Computer Science Engineering Experience – 7+ years We are looking for a highly skilled and experienced Design Verification Engineer to join our team. This role is ideal for someone who brings deep technical expertise in verification along with a strong grasp of industry protocols and low-power design techniques. You'll work on advanced IP and SoC subsystems involving both RISC-V and ARM-based architecture, and collaborate closely with our architecture, design, and validation teams. What You'll Do: Own and drive the full verification cycle for IP blocks and subsystems Create detailed verification plans, identify test items, and track coverage Build UVM-based test benches from scratch, including drivers, monitors, and scoreboards Perform low power verification using both UPF and Native Low Power (NLP) methods Develop and run UVM-based test environments for Ethernet and other protocol interfaces Integrate and work with third-party Verification IPs (VIPs) Write and debug assertions and functional coverage models Collaborate with design and architecture teams to close verification cycles efficiently Support silicon bring-up and post-silicon debug when required Mentor junior team members on verification techniques and best practices Key Skills We Are Looking For: UPF / Low Power Verification (UVM expert) Strong understanding of low-power concepts in ASIC design (UPF/NLP) from a verification perspective UVM with Ethernet protocol expertise NLP Testbench Verification with Native Low Power (UVM expert) Strong command over System Verilog , Verilog , and UVM methodology Solid understanding of ASIC design flows and power-aware design concepts Experience with protocols like PCIe, AXI, CHI, Ethernet, USB, NVMe, DDR, and CXL Good working knowledge of System Verilog Assertions (SVA) and formal verification techniques Hands-on experience with scripting ( Python, Perl, Shell, TCL ) Comfortable working in Linux development environments Excellent debugging, problem-solving, and analytical thinking Strong communication and collaboration skills Qualifications: Bachelor’s degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, Computer Science, or related fields Fluent in both written and spoken English Excellent collaborative skills Highly motivated and self-driven individual Strong coding and object-oriented programming skills Excellent debugging, problem solving, and analytical skills Knowledgeable in digital design Minimum 7 years of industry experience in Design Verification roles. A track record of successfully verifying complex IP blocks or subsystems from spec to silicon.

You should have 10+ years of hands-on experience in FPGA design and development using Verilog/VHDL. Your background should include a strong understanding of synthesis, place & route, timing analysis, and bitstream generation. Proficiency with FPGA tools like Vivado, Quartus, Synplify, etc. is necessary. It is essential to have solid hands-on experience with Wi-Fi MAC/PHY integration or validation. You should be capable of supporting firmware teams and providing system-level debug support. Experience with lab tools such as oscilloscope, logic analyzer, JTAG, etc. will be beneficial. You must possess excellent debugging, analytical, and communication skills. The expected Notice Period for this position is Immediate to 30 days. If you are interested in this opportunity, please share your resume to the email address sushma.vunnam@modernchipsolutions.com.,