2715 Verilog Jobs - Page 7

Position: Project Lead – MEO SATCOM Network & SCPC Platform Integration Location: Bangalore, KA Duration: 6+ months Mode: 3 days onsite We are seeking a dynamic and technically astute Project Lead to manage a cutting-edge satellite communications initiative supporting a Medium Earth Orbit (MEO) constellation designed for third-party SATCOM network hosting. This program is a strategic response to defense industry demand for extending existing modem capabilities beyond traditional GEO environments. The project will deliver a DVB-S2X-based SCPC solution using 450mp modems, integrated at both hub and terminal levels, and supporting OpenAMIP and OpenBMIP protocols for seamless terminal mobility and control within the MEO network architecture. This role requires full ownership of the project lifecycle—from planning through execution—while providing hands-on technical leadership and oversight to a blended across both US and India. Lead the design, integration, and deployment of SCPC modem systems compatible with a generic MEO network infrastructure. Manage cross-functional teams developing: Microservices in Go, Python, and other languages. External APIs using GraphQL and internal services using RESTful APIs. Embedded system components in C++, Go, and Python. Oversee design and verification of FPGA-based DSP algorithms using Verilog, System Verilog, or VHDL targeting Xilinx/Altera platforms. Coordinate efforts involving OpenAMIP and OpenBMIP integration for automated terminal configuration and mobility support. Drive system validation and automation testing using tools such as Behave/Cucumber, Jira, Bitbucket, Jenkins, Artifactory, and Docker. Required Qualifications: 8+ years of experience in software development and architecture. 5+ years of experience leading projects of similar complexity and scope

NVIDIA has been redefining computer graphics, PC Gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s motivated by phenomenal technology – and outstanding people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. The HWPM Team at NVIDIA is seeking an excellent ASIC Verification Engineer to drive high-quality, robust verification of system-level IP across unit, subsystem, and SoC levels. This role is ideal for someone passionate about ground-breaking hardware, sophisticated verification methodologies, and crafting the future of computing. Come join the team and see how you can make a lasting impact on the world. What You’ll Be Doing Play a key role in the Hardware Performance Monitor (HWPM) team, helping define and develop system-level RTL and performance measurement methodologies for NVIDIA’s industry-leading SoCs and GPUs. Develop comprehensive test plans, implement tests, and apply robust verification strategies to validate microarchitecture and design functionality. Design and implement reusable, scalable testbenches and testbench components using System Verilog and UVM. Collaborate with architects, RTL designers, and software engineers to drive feature completeness, performance visibility, and verification closure. What We Need To See M.Tech. (or equivalent) in VLSI or Electronics Engineering OR B.Tech with 2+ years of experience in a similar domain Hands-on experience in unit and/or system level verification Ability to contribute to testbench development and maintenance, preferably using System Verilog and standard methodologies Proficiency in Python or industry-standard scripting languages for automation and test development Proven debugging fundamentals — ability to read waveforms, analyze logs, and isolate issues effectively Familiarity with industry-standard tools such as VCS, Xcelium, Verdi, or similar simulation/debug environments Good understanding of RTL design concepts and experience working with Verilog or SystemVerilog Experience with UVM (Universal Verification Methodology) is a strong plus Clear communication skills and collaborative attitude, with ability to work alongside design, DV, and automation teams Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. Also, e have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our outstanding engineering teams are growing fast. If you are creative, curious, and motivated with a real passion for technology, we want to hear from you! JR2000528

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve. The Opportunity As a Senior Principal Analog Design Engineer at Allegro MicroSystems, you will be a pivotal technical leader within our design organization. You will leverage your deep expertise in analog integrated circuit design to drive the development of highly complex and innovative solutions for our next-generation products. This role requires not only exceptional technical acumen but also the ability to mentor junior engineers, define architectural strategies, and significantly influence product roadmaps. You will tackle the most challenging design problems, contributing directly to Allegro's market leadership and technological advancements. What You Will Do Lead the architecture, design, simulation, and verification of complex analog and mixed-signal circuits for high-performance integrated circuits, from concept to mass production. Drive the definition of circuit specifications, block-level partitioning, and top-level integration strategies. Perform advanced circuit analysis, modeling, and simulation using industry-leading EDA tools (e.g., Cadence Virtuoso, Spectre, AMS, Verilog-A/AMS). Provide technical leadership and mentorship to less experienced engineers, fostering their growth and ensuring design quality across the team. Collaborate closely with system architects, digital design engineers, layout engineers, test engineers, and product marketing to ensure successful product realization. Develop and implement innovative design techniques and methodologies to achieve aggressive performance, power, and area targets. Lead design reviews, critically evaluating designs, providing constructive feedback, and ensuring robust design practices are followed. Oversee silicon characterization, debug, and validation activities, driving root cause analysis for complex issues. Contribute to intellectual property generation through invention disclosures and patent applications. Stay abreast of the latest industry trends, technologies, and competitive landscape, applying this knowledge to influence future product definitions and technology roadmaps. What You Will Bring Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field. Typically 10+ years of progressive experience in analog integrated circuit design, with a proven track record of successfully bringing complex ICs to market. Deep expertise in the design of a wide range of analog building blocks, such as high-performance op-amps, ADCs/DACs, PLLs, bandgap references, LDOs, power management circuits, and sensor interfaces. Extensive experience with advanced semiconductor process technologies, including BCD (Bipolar-CMOS-DMOS) and deep sub-micron CMOS processes. Proficiency with a full suite of EDA tools for schematic capture, simulation, layout, and verification (e.g., Cadence Virtuoso, Spectre, AMS, Calibre, Quantus). Strong analytical and problem-solving skills, with the ability to tackle complex technical challenges independently and collaboratively. Demonstrated leadership capabilities, including mentoring, technical guidance, and influencing cross-functional teams. Excellent communication skills, both written and verbal, with the ability to present complex technical information clearly and concisely. Ability to work effectively in a fast-paced, dynamic environment and manage multiple priorities.

Hiring_Asic_Verification_Product_Company Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. The solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and looking forward to playing a significant role in it. Experience 5-20Years This is what you are responsible for Develop verification environments for modules, subsystems, top level and FPGA Build models, checkers and random test frameworks using SystemVerilog and UVM Participate in Low power analysis (UPF), power estimation, C modeling Perform lint, CDC, code coverage, functional coverage Formal verification of modules using SVA assertions Necessary Qualifications Experience in verifying complex subsystems and ASICs Experience with building scalable verification environments from scratch Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc. Exposure to FPGA emulation platforms, silicon bringup, and board debug BTech/MTech in EE/CS with any level of experience Please do reach me on +91-9071106778

We are looking for experienced Senior/Lead Emulation Verification Solution Development Engineer passionate about developing cutting-edge emulation solutions for our team. Does this sound like a good role for you? Senior/Lead Emulation Verification Solution Development Experience : 5yrs to 10 years Location: Bangalore & Noida Job Description: Proficiency in C/C++ programming and object-oriented programming concepts. Good understanding of digital design principles and HDL languages such as System Verilog and Verilog. You are familiar with any of the industry standard protocols like AXI, AMBA, JTAG, AVB, CAN, TSN, Ethernet, PCIe, CXL, UCIe, UCIE, UFS, HDMI, DRAM, MMC protocols for semiconductor customers. Knowledge of ARM architecture, UVM, and functional verification, along with experience in emulation, will be a significant advantage. You thrive in collaborative environments, have excellent communication skills, and are adept at solving complex problems. Your ability to interact with customers during deployment and debug processes will ensure successful implementation and satisfaction. B.E/B.Tech/M.Tech in Electronic & Communication or Computer Science Engineering is essential. What You’ll Be Doing: Developing emulation solutions for industry Standard protocols such as AXI, AMBA, JTAG, AVB, CAN, TSN, Ethernet, PCIe, CXL, UCIe, UCIE, UFS, HDMI, DRAM, MMC protocols for semiconductor customers. Engaging in software development using C/C++ and synthesizable RTL development with Verilog. Verifying solutions to ensure high performance and reliability. Interacting with customers during the deployment and debug phases to ensure smooth implementation. Collaborating with cross-functional teams to integrate emulation solutions. Maintaining and enhancing existing emulation solutions to meet evolving industry standards. Please share your updated CV to taufiq@synopsys.com or refer who would like to explore this opportunity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

You will be responsible for contributing to the development and implementation of advanced electronic systems as an Electronics Design Engineer. Your role will involve working with technologies like FPGAs and ASICs, designing integrated circuits (ICs) and printed circuit boards (PCBs), and innovating methods for efficient electrical power usage and electronic equipment design. The ideal candidate for this position will have a strong foundation in electronic engineering principles and practical experience with hardware design tools and simulation environments. Your primary responsibilities will include designing, simulating, and implementing digital logic using FPGA and ASIC technologies, developing and verifying layouts for ICs and PCBs using industry-standard tools, collaborating with cross-functional teams to integrate electronic systems into larger platforms, conducting testing, debugging, and validation of electronic components and systems, optimizing power usage and performance of electronic equipment, and documenting design processes, test results, and technical specifications. Your primary skills should include proficiency in VHDL/Verilog for FPGA/ASIC development, experience with PCB design tools such as Altium Designer, Cadence, or Mentor Graphics, knowledge of IC design and verification methodologies, and a strong understanding of electronic circuits and power systems. Additionally, familiarity with embedded systems and microcontroller programming (e.g., ARM, PIC), experience with simulation tools like SPICE or ModelSim, basic understanding of signal integrity and thermal analysis, as well as good communication and teamwork skills will be advantageous secondary skills for this role. To qualify for this position, you should hold a Bachelors or Masters degree in Electronics Engineering, Electrical Engineering, or a related field.,

Responsibilities Develop synthesizable RTL for high-performance SoC, subsystem, or IP designs APB Contribute to architecture definition, micro-architecture design, and implementation Collaborate closely with architecture, verification, and physical design teams ARM Own and deliver RTL blocks from spec to tape-out Ensure clean handoff of RTL to verification and synthesis Support post-silicon bring-up and debugging, if required Mandatory Requirements 5-10 years of hands-on RTL design experience in production-grade projects At least 3 full-cycle design projects (preferably SoC, subsystem, or IP level) Strong expertise in Verilog/SystemVerilog RTL coding Solid understanding of digital design principles including clocking, resets, data-path control, pipelining, etc. Exposure to design closure flow including synthesis and timing closure support Familiarity with AMBA (AXI, AHB, APB) or similar interconnects Experience working in cross-functional engineering teams Good understanding of synthesis, STA, and backend interactions Strong problem-solving and debugging skills Excellent communication and documentation capabilities (ref:hirist.tech)

We are seeking a highly motivated and experienced Embedded Engineer with 2 to 3 years of hands-on experience in embedded systems development. As an Embedded Engineer, your primary responsibility will involve designing, developing, testing, and maintaining embedded software and firmware for cutting-edge products across various industries. This role requires close collaboration with hardware engineers, product managers, and cross-functional teams to ensure seamless system integration with a focus on quality and efficiency. Your key responsibilities will include designing, developing, and maintaining embedded software and firmware for microcontroller/microprocessor-based systems. You will work closely with hardware teams to define system architecture, refine requirements, and establish interfaces. Ensuring robust and optimized code for real-time embedded systems within resource and timing constraints is essential. Additionally, you will be debugging integration issues, participating in architecture discussions, and contributing technical solutions. Maintaining technical documentation, conducting testing and verification processes, optimizing code efficiency, and staying updated on industry best practices are crucial aspects of this role. To qualify for this position, you should hold a Bachelors or Masters degree in Electronics & Communication, Electrical Engineering, or a related field. You must have 2 to 3 years of experience in software/firmware development for embedded systems. Proficiency in C and C++ programming for embedded platforms is required, with exposure to assembly language considered advantageous. A strong understanding of real-time operating systems, embedded architectures, and communication protocols such as UART, SPI, and I2C is necessary. Experience with embedded development tools, hardware-software integration, low-level driver development, and version control systems is highly desirable. This is a full-time position with benefits including Provident Fund. The role is based in Vijayawada, Andhra Pradesh, requiring reliable commuting or willingness to relocate. The ideal candidate will possess solid problem-solving skills, attention to detail, clear communication abilities, and a collaborative approach to working in cross-functional teams. Experience with safety-critical or security-focused embedded systems would be a valuable asset.,

Looking for Siemens EDA ambassadors: Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We Make Real What Matters. This is your role. Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 4-7 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform the everyday! #DVT

Hughes Systique Corporation (HSC) , a leading global digital solutions and service provider, is expanding its team in Dehradun, Uttarakhand . This is a great opportunity for FPGA Design Engineers to work on cutting-edge projects with a multinational company—right here in Dehradun. IKSANA is supporting HSC in this recruitment. About Hughes Systique Corporation (HSC) HSC is a multinational company delivering innovative solutions in Networking, AI & ML, Retail, Automotive, IoT, Blockchain, and Security. The team includes world-class domain experts, system architects, and engineers working with global clients on challenging, innovative, and impactful projects. Role : FPGA Design Engineer Location : Dehradun (Full-Time, On-Site) Experience : 3-6 Years Type : Permanent Openings : 2 Note : This is a Dehradun-based position only. Open to candidates currently in Dehradun, as well as professionals from Dehradun who are looking to relocate back. Required Skills : FPGA Design and Development Verilog and/ or VHDL Xilinx Vivado tools ModelSim and UVM Educational Background : Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field Role Overview : HSC is seeking experienced FPGA developers to join their team in Dehradun to work on the design, development and optimisation of complex FPGA-based systems for a variety of applications. The ideal candidate will have a strong background in FPGA design, verification, and implementation, as well as experience working with hardware and software engineers to integrate FPGA designs into larger systems. The candidate should have exposure to the latest FPGA technologies and techniques. If you have strong FPGA design expertise and want to join a company that values learning, innovation, and career growth, we’d like to connect with you. To Apply: Send your CV to aayushi@outlookwork.com Aayushi Sharma: +91 80063 07272

Bangalore,Karnataka,India Job ID 771289 Grow with us About this Opportunity: We are looking for an FPGA Designer to join the Ericsson Silicon organization. You will work with a group of dedicated engineers passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team—developing and integrating complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, you'll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork. You will: Design and implement FPGA-based Radio and RAN Compute solutions Develop and optimize FPGA designs for performance, power, and cost-efficiency Collaborate with hardware and software engineers to integrate FPGA solutions into larger systems Apply industry-standard tools and methodologies for FPGA development and implementation Research and stay updated on the latest advancements in FPGA technology, including academia and industry trends in AI and Machine Learning Document design specifications, test procedures, and results Participate in design reviews and contribute innovative ideas to improve FPGA solutions To be successful in the role you must have: 5+ years of experience in FPGA development Comprehensive knowledge of: FPGA technology, design environments, and design methodologies FPGA design tools (e.g., Vivado, Quartus, or similar) Hardware description languages (HDL), such as Verilog or VHDL Experience with various communication protocols—DDRX, AXI4, PCIE, SPI, I2C, embedded processing Experience with scripting languages such as Python, Tcl, shell scripting, etc. Familiarity with hardware architecture and digital signal processing Excellent problem-solving and analytical skills Excellent English verbal and written communication skills High self-motivation and the ability to work independently while being a great teammate A track record of successful cross-team and cross-site cooperation A Master's degree in Electrical or Computer Engineering or equivalent

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in using ASIC development tools such as Lint, CDC, Design compiler, and Primetime is necessary. An understanding of constraint development and timing closure will be a plus. Experience in Synthesis and knowledge of timing concepts will also be beneficial. Additionally, experience in creating padring and collaborating with the chip-level floorplan team is desirable. You must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of relevant experience or a PhD with 4+ years of relevant experience will also be considered. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities in the hiring process. The company expects all employees to adhere to relevant policies and procedures, including security protocols and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to submit profiles, applications, or resumes through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers.,

NVIDIA, a company known for continuously reinventing itself, has played a pivotal role in reshaping the PC gaming market, modern computer graphics, and parallel computing with the invention of the GPU. The realm of artificial intelligence is currently experiencing significant growth globally, necessitating highly scalable and massively parallel computation capabilities where NVIDIA GPUs excel. NVIDIA's commitment lies in addressing challenging problems that have a profound impact on the world, ultimately aiming to enhance human creativity and intelligence. As part of the NVIDIA team, you will find yourself in a diverse and supportive environment that fosters inspiration and excellence, encouraging everyone to deliver their utmost potential. Join our team to leave a lasting imprint on the world! The NVIDIA System-On-Chip (SOC) group is seeking a talented Senior SOC Design Engineer to contribute to the development of complex chips that now incorporate tens of billions of transistors to meet the escalating computational demands. We are looking for a standout candidate with a strong affinity for RTL integration and chip-level front-end design, encompassing elements such as padring, pinmuxing, SOC Assembly process, retiming, and more. Your role will involve a genuine enthusiasm for methodologies and automation solutions that facilitate SOC creation in the most efficient manner. In this capacity, you will have the opportunity to participate in the construction of advanced Tegra SOCs, collaborating closely with chip management to establish ASIC execution timelines and objectives, while engaging directly with various teams including System Architecture, unit-level ASIC, Physical Design, CAD, Package Design, DFT, and others. Furthermore, you will contribute to defining and refining methodologies that will enable the development of more streamlined and adaptable SOCs in the future. **What you'll be doing:** - Drive SOC Assembly and design chip-level functions for Tegra SOCs. - Ensure front-end design quality and correctness through checks, reviews, and collaboration with multi-functional teams. - Lead SOC execution across chip milestones, working in coordination with various teams to define, track, and manage intricate dependencies. - Develop and implement system-level methodologies, tools, and IPs to streamline SOC development in an efficient and scalable manner. - Identify and address challenges and inefficiencies in the front-end chip implementation process, proposing and implementing solutions to enhance effectiveness. **What we need to see:** - B.Tech or M.Tech in Electronics Engineering. - 5+ years of demonstrated experience in chip design, with a focus on SOC integration and design automation. Knowledge of padring and fuse/floorsweep design is advantageous. - Strong analytical and problem-solving abilities. - Proficiency in RTL design (Verilog), System-On-Chip design/implementation flow. - Proficient in coding with Perl, Python, or other standard scripting languages. - Exposure to diverse Chip Design Functions to collaborate and resolve complex multi-functional challenges. - Excellent interpersonal skills to engage with multiple teams effectively and drive consensus. - Strong teamwork and collaboration skills with fellow team members. - Background in SOC Verification, Synthesis, Physical design, and DFT is a plus. - Experience in RTL Build flows and Makefiles is beneficial.,

About QpiAI: QpiAI is at the forefront of discovering optimal AI and Quantum systems across various industries including Life sciences, Healthcare, Transportation, Finance, Industrial, and Space technologies. Specializing in building full stack Enterprise Quantum Computers, the Quantum hardware team at QpiAI is dedicated to the design and characterization of Quantum Processor, Cryogenic Quantum Control Circuits, RF Control Hardware, and QpiAI ASGP. We are looking for a talented Hardware Design Engineer to join our innovative team. Together, we aim to develop cutting-edge custom hardware for Quantum computers that have the potential to revolutionize various sectors. If you are a self-driven individual with a solid grasp of building complex SOC and IPs, possess a deep understanding of client requirements, and are familiar with different development cycles, then this opportunity is tailored for you. Responsibilities: - Engage in micro-architecture development and document specifications. - Implement designs in RTL and collaborate with the verification team to ensure functionality. - Utilize logic design expertise to optimize performance and power objectives. - Produce a synthesis/timing clean design while cooperating with the physical design team for a routable and physically implementable design. Requirements: - Bachelor's degree in electrical engineering or computer engineering. - 3+ years of experience in chip design development for complex designs. - Proficiency in logic design, Verilog, and/or System-Verilog, with a strong understanding of physical design and VLSI. - Excellent interpersonal skills and a team player mindset. - Familiarity with design reuse, including RTL, constraints, and waiver. - Experience in handling timing constraints and exceptions. - Ability to conduct standard quality checks such as LINT and CDC. Join us at QpiAI and be part of a dynamic team driving advancements in Quantum computing hardware to shape the future of technology across multiple industries.,

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. This entails supporting all leading DDR memory protocols including DDR4/LPDDR4. You will collaborate on working with the existing RTL, incorporating new features, ensuring customer configurations are clean during verification regressions, providing customer support, and ensuring the design adheres to LINT and CDC design guidelines. To qualify for this role, you should hold a BE/B.Tech/ME/M.Tech in Electrical/Electronics/VLSI and possess significant experience as a design and verification engineer, with a focus on RTL design and development. Proficiency in RTL Design using Verilog is essential, while experience with System Verilog and familiarity with UVM based environment usage/debugging are also required. AXI3/4 experience is desired, and prior exposure to DDR Memory controller and protocol is highly desirable. Having prior experience in RTL design and implementation of complex protocols, as well as in IP development teams, would be advantageous. Join us at Cadence, where we hire and develop leaders and innovators who strive to make a significant impact on the world of technology. Together, let's tackle challenges that others cannot solve.,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dedicated and detail-oriented Formal Verification Engineer with a passion for ensuring the reliability and functionality of complex design IPs. You excel in a collaborative environment, working closely with designers, architects, and verification engineers to drive verification projects to success. You possess a solid understanding of hardware micro-architecture and design, and you are proficient in HDLs like Verilog and SystemVerilog. Your problem-solving skills are top-notch, and you are familiar with formal property verification concepts and tools. You are eager to contribute to a team that is at the forefront of technological innovation and excellence. What You’ll Be Doing: Helping decide on the best applications of formal verification techniques to various parts of the design. Reviewing functional and micro-architectural specifications to define the scope for formal verification. Creating high-quality formal verification test plans to sign off on the corresponding design implementation. Building formal verification testbenches, coding assertions and constraints, and applying abstraction techniques. Applying formal coverage techniques to analyze over-constraints and measure functional coverage. Collaborating closely with the Synopsys Tool Development Group to drive verification projects. The Impact You Will Have: Ensuring the reliability and functionality of complex design IPs through rigorous formal verification. Contributing to the development of high-quality IP that meets the stringent requirements of our clients. Driving innovation in verification methodologies and techniques. Collaborating with a talented team to achieve project milestones and goals. Enhancing the overall quality and performance of Synopsys' product offerings. Playing a key role in the success of various high-profile projects within the company. What You’ll Need: Pursuing or completed BTech/MTech degree in Electrical Engineering, Computer Engineering, or a related field. Good understanding of hardware micro-architecture and design. Proficiency in HDLs like Verilog and SystemVerilog. Familiarity with SystemVerilog Assertions (SVA) and basic concepts of formal property verification. Good debugging and problem-solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal and communication skills and a dream to work as a great team member. Who You Are: An excellent communicator who can articulate complex ideas clearly and effectively. A team player who thrives in a collaborative environment. A detail-oriented individual with strong analytical and problem-solving skills. A proactive learner who stays updated with the latest industry trends. A highly motivated and driven professional with a passion for technology. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on formal verification engineering. Our team is dedicated to ensuring the reliability and functionality of complex design IPs through rigorous verification methodologies. We value collaboration, creativity, and excellence, and we are committed to pushing the boundaries of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

You have a unique opportunity to join Astera Labs, a global leader specializing in purpose-built connectivity solutions that unleash the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform seamlessly integrates PCIe, CXL, and Ethernet semiconductor-based solutions along with the COSMOS software suite, offering a software-defined architecture that is not only scalable but also customizable. Building on strong relationships with hyperscalers and the data center ecosystem, we are at the forefront of innovation, delivering flexible and interoperable products that are transforming modern data-driven applications. Explore more about our groundbreaking work at www.asteralabs.com. As a candidate, you should possess a Bachelor's degree in electrical engineering (EE), with a preference for a Master's or Ph.D. in EE, accompanied by a background in Math or Computer Science. You should have a minimum of 8 years of experience in formal verification or 7 years in traditional design verification (DV). A strong work ethic, adept at managing multiple tasks in a dynamic environment, is essential. Your ability to plan for customer meetings, work independently, and exhibit an entrepreneurial mindset with a customer-centric approach are key attributes. Proficiency in cross-functional collaboration is also vital for this role. Your responsibilities will include developing detailed formal verification (FV) test plans based on design specifications and collaborating with design teams to enhance micro-architecture specifications. You will identify crucial logic components and micro-architectural properties to ensure design correctness. Implementing formal verification models, abstractions, and assertions, utilizing assertion-based model checking to detect corner-case bugs will be part of your role. You will apply complexity reduction techniques, develop scripts for enhanced productivity, and assist in implementing assertions and formal verification testbenches for RTL at unit/block levels. Your involvement in design reviews and collaboration with design teams to optimize design quality based on formal analysis feedback will be crucial. Proficiency in System Verilog/Verilog and scripting abilities with Python or Perl are required. Preferred candidates will have hands-on experience with formal verification tools like Synopsys VCFormal and Cadence JasperGold, along with familiarity in automating formal verification workflows within a CI/CD environment. At Astera Labs, we value diversity and inclusivity, believing that creativity and innovation thrive in a team with varied ideas, backgrounds, and experiences. We actively encourage individuals with diverse backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and persons with disabilities, to apply and be part of our dynamic team.,

As a Sr. Engineer in ASIC Verification at Synopsys, you will play a crucial role in ensuring the robustness and reliability of our digital designs through meticulous verification processes. Your expertise in high-speed protocols and strong foundation in Verilog, VHDL, and/or SystemVerilog will empower you to identify verification environment requirements and develop complex UVM verification environments. Your proactive approach to problem-solving and excellent communication skills will enable you to collaborate effectively with cross-functional teams and contribute to the success of our cutting-edge projects. Your responsibilities will include generating verification test plans, defining and verifying complex UVM verification environments, evaluating various aspects of the development flow, and identifying design problems to propose corrective actions. By enhancing the overall quality and performance of our silicon IP products, you will help drive continuous improvements in our verification methodologies and practices. Your passion for learning and exploring new technologies, coupled with your 3+ years of relevant experience in ASIC digital verification, will be instrumental in supporting the growth and success of both our projects and Synopsys as a whole. You will be part of an experienced and dedicated digital design and verification team at Synopsys, where excellence and continuous improvement are key priorities. Working in a dynamic and fast-paced environment, you will have the opportunity to collaborate with experts in various fields, learn from their insights, and contribute significantly to the success of our innovative projects. If you are a detail-oriented, innovative engineer with a proven desire to explore new technologies and a proactive approach to addressing challenges, we invite you to join us in shaping the future through continuous technological innovation. In return for your contributions, we offer a comprehensive range of health, wellness, and financial benefits tailored to meet your needs. Your recruiter will provide detailed information about the salary range and benefits during the hiring process. If you are ready to make a meaningful impact in the Era of Smart Everything, we look forward to welcoming you to our team at Synopsys.,

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: THE ROLE: This role will be part of Silicon Applications and Documentation engineering team in AECG. You will be working with a collaborative team focused on enabling customers to succeed when using ACAP/FPGA. You will have the opportunity to focus on Complex IPs and memory interfaces on the ACAP/FPGA platforms for specialty applications such as image sensors, IOT, emulation etc... In this cross-functional position you will interface directly with Design and Software engineering groups, and you will be the primary interface between the engineering teams and escalated customer support issues. THE PERSON: You are a team player who has excellent communication and writing skills. You have experience communicating effectively and working optimally with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are interested in debugging customer issues and leading complex projects. KEY RESPONSIBILITIES: As a member of this team, you will be responsible for the following: Creating customer documentation (datasheets, architecture manuals, product guides, errata, tutorials) Validating and characterizing memory/IO interfaces and other FPGA key features Building custom designs using Verilog, SystemVerilog or VHDL Resolving escalated customer support issues PREFERRED EXPERIENCE: Excellent written and verbal communication skills. Effective project planning and execution FPGA or ASIC design background Strong background in memory interfaces Experience in Silicon Bring-up and Hardware debug Strong background in RTL development and verification Familiarity with programming/scripting language ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Product Engineer (PE) bridges the gap between customers, R&D, and field Application Engineers (AEs). In this highly creative and innovative role, they are responsible for ensuring that existing flows and apps meet the ongoing needs of our customers, while also developing flows and requirements to solve new verification challenges. The PE will collaborate closely with both customers and R&D to drive specification, implementation, and evaluation/benchmarking of the new solutions. In addition, the PE will be responsible for the roll-out of new features to AEs and customers, and in some cases will play a pivotal role performing hands-on work (remote or onsite) to enable key customers to achieve their verification goals with very high performance and efficiency. This position gives abundant exposure to working on and influencing the latest design styles and verification methodologies used by large semiconductor companies. It may occasionally involve worldwide travel to attend meetings or conferences or to assist with product demonstrations, evaluations, and competitive benchmarks at customer sites. Desired Technical Skills and Experience The candidate should possess a BE/B.Tech engineering or higher degree in CS or EE with a minimum 10 years of industry experience. Minimum of 4 years hands-on experience in applying formal property verification technologies and methodologies. Hands-on design experience using Verilog, System Verilog is a must. Hands-on experience with any of the common scripting languages, such as TCL, Perl, Python, etc., is a must. Desire/Ability to learn complex arithmetic algorithms is a must. Hands-on Jasper experience is a plus. Knowledge of arithmetic algorithms (various multiplier implementations like Booth, compression schemes, dividers like SRT, floating point operations) is a plus. Working knowledge of C++ is a plus. Hands-on experience with formal software verification is a plus. Hands-on experience using HDL simulator is a plus. Knowledge of sign-off methodologies using code & functional coverage is a plus. Desired Soft Skills and Experience Highly organized, self-motivated individual with demonstrated ability to multitask Very good communication skills and a strong desire to work in a global environment with customers, developers, marketing, and sales. Passionate about adopting and promoting new technologies and making customers successful. Successful in building and delivering training content on rolling out new products/methodologies. Highly technical & hands on engineer with an ability to partner with key customers and provide expert support to field application engineers. We’re doing work that matters. Help us solve what others can’t.

MIPS is looking for a highly experienced and motivated Engineering Manager to lead the CPU team. In this critical role, you will manage a team of skilled engineers dedicated to developing high-performance CPU cores based on the RISC-V architecture. Your responsibilities will include overseeing the entire RTL design lifecycle, ensuring technical excellence, innovation, and timely delivery. You will lead and mentor a team of microarchitecture and RTL design engineers focused on high-performance CPU core development. Your role will involve driving the design execution of CPU subsystems, meeting performance, power, area, and quality goals. You will be responsible for creating and refining microarchitecture specifications and RTL designs for CPU core components, collaborating with various teams to ensure efficient implementation, optimizing design methodologies for scalability and quality, and fostering a culture of innovation and technical excellence. The ideal candidate should have a Master's or PhD in Electrical Engineering, Computer Engineering, or a related field, with at least 15 years of experience in silicon or CPU design, including 5+ years in a management role. A proven track record of successfully delivering complex CPU blocks or subsystems, deep understanding of microprocessor design principles, strong technical knowledge in RTL design, and experience with project management and organizational skills are required. Preferred qualifications include experience with RISC-V, MIPS, or ARM CPU cores, familiarity with advanced CPU design concepts, working in a globally distributed environment, proficiency with EDA tools and scripting languages, and modern design methodologies. Joining MIPS offers you the opportunity to work with a dynamic and fast-growing team that is shaping the future of high-performance RISC-V processors. With small, agile teams and a flat organizational structure, you will have a direct impact on cutting-edge technology and product direction. MIPS provides an autonomous and empowering work culture, the chance to collaborate with industry-leading engineers, competitive compensation and benefits, and a platform for career growth in the exciting RISC-V ecosystem.,

Job Location: Hyderabad Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI Preferred Experience: Should have worked on Processor based System or Sub-system level verification Hands on experience with assembly, UVM, SV, C++ Experience in developing complex test bench/model in UVM, Verilog, System Verilog Hands on experience in developing test plans, coverage closure Ability to code readable, maintainable and verifiable code using UVM, SV, Strong digital design concepts Experience in developing asm/C++ tests will be an added advantage Experience in Power Management, Clock, Reset will be an added advantage Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage

GlobalFoundries is currently seeking a highly motivated Memory Design Engineer to join the Memory IP group in the Global Organization, located in Bangalore. In this role, you will be responsible for developing CMOS memories such as SP SRAM, DP SRAM, Register File, and ROM. Your tasks will include circuit design, simulation, margining, and characterization of full custom circuits, as well as functional simulations and statistical analysis. You will also be involved in verifying bit cells, physical layout design and verification, and signing off and releasing the memory IPs on dedicated IP validation test chips. Additionally, you will support silicon bring-up and characterization, participate in implementation & design/layout reviews, and contribute innovative ideas for addressing design problems. Collaboration with IP design and layout teams will be a key aspect of this role. The ideal candidate should hold a Bachelors/Master's degree in Electrical (VLSI, Microelectronics, or related fields) from a reputable university with a minimum of 4-12 years of work/industry experience. Proficient knowledge and experience with EDA tools such as Cadence, Mentor Graphics, and Synopsys for schematic design & simulations are required. Experience in SRAM Memory designs, timing characterization, and Verilog is desirable. General analog mixed-signal design concepts knowledge is also preferred. Strong technical verbal and written communication skills are essential, along with the ability to work effectively with cross-functional teams. Preferred qualifications include knowledge in various technologies (Bulk, CMOS & SOI) process, hands-on experience with state-of-the-art memory or analog design flows, and programming skills applicable to design flow automation tasks. The ability to work within a dynamic interdisciplinary environment, knowledge of different technology nodes, and proficiency in communicating and working efficiently in an international multi-disciplinary setting are advantageous. Strong analytical and problem-solving skills are a must. GlobalFoundries is an equal opportunity employer that values diversity and inclusion in the workplace. We believe that a multicultural environment enhances productivity, efficiency, and innovation, while ensuring that all employees feel respected, valued, and heard. For more information about our benefits, please visit: https://gf.com/about-us/careers/opportunities-asia,

To apply to a Varex Imaging position, please create an account and sign-in. CURRENT VAREX IMAGING EMPLOYEES: Please apply by logging into your internal Workday Account. Analyzes, designs, programs, debugs and modifies FPGA code designs. Troubleshoots code for firmware (IC embedded code) applications. Work often involves analog and digital hardware and software operating systems. Position requires knowledge and exposure to hardware design. Typically, programs in - Hardware Description Languages (e.g., SystemVerilog or VHDL) or high-level languages (e.g., Python). FPGA / Embedded Firmware Engineer (Firmware Engineer III) Varex Imaging is seeking a FPGA / Embedded Firmware Engineer in the fast-growing X-Ray Imaging Components division. This individual will work in our India facility. The developer will bring value to the team by developing firmware systems and libraries needed to process and manage flat panel x-ray detectors data used in medical and industrial imaging systems. Candidates are expected to thrive in a fast-paced, self-directed environment and work both individually and with a team of highly skilled FPGA engineers. Responsibilities include writing HDL code, developing/implementing efficient algorithms interacting with x-ray hardware components, and developing low-level component interfaces in both FPGA and embedded software. Your Role: - Experience with Verilog, SystemVerilog, and/or VHDL - Knowledge of FPGA development basics - Familiarity with simulation tools like Modelsim or equivalent - Proficiency in a scripting language such as Python - Some experience with debugging electrical hardware using Chipscope/Signaltap or oscilloscope/logic analyzer Your Profile: - B.S. in Electrical Engineering, Physics, Computer Science, or related field with 5+ years of relevant experience, or M.S. or Ph.D. with 2+ years of relevant experience - Experience with Windows & Linux - Familiarity with Object-oriented Design and Analysis (OOA and OOD) is a plus - Ability to develop specifications & requirements - Design, build, and unit test firmware in a collaborative environment - Knowledge/use of automated test benching is beneficial - Familiarity with the use of FPGA intellectual property is advantageous - Excellent oral and written communication skills - Must be able to work with minimal supervision - Proficient in utilizing business tools such as E-mail, Microsoft Word, Excel, and PowerPoint What we offer: - A unique opportunity to become part of a growing organization in India within a global market leader in X-ray imaging components - Excellent development potential - An international work environment with global teams collaborating on various projects across multiple countries - Competitive compensation package including participation in Varex incentive plans - Corporate Health Benefits - Additional benefits will be added as we grow Time Type: Full time Job Type: Regular Work Shift: N/A Salary: Not specified,

Become a Pioneer in Computing - Join Vicharak! At Vicharak , we stand at the vanguard of a computing revolution. Similar to the trailblazers at Bell Labs in 1947 who witnessed the birth of the transistor, we're revolutionizing the future of semiconductors through innovative FPGA technology. Unlike traditional processors, our FPGAs enable programmable changes in inner circuitry, unlocking new dimensions in parallelism, speed, and computing. Our groundbreaking VAAMAN hardware system, combining FPGA and SBC, epitomizes our innovation, and we're searching for talented individuals who share our fervor for this field. We invite researchers, developers, designers, engineers, and architects to join us in crafting the next era of computing. What You'll Learn: Software languages: C/C++, Python, HDL languages like Verilog and System Verilog. Utilize diverse tools, including compilers such as GCC and X86s, alongside IDEs like Visual Studio and PlatformIO. Master FPGA tools like Vivado, Radiant, and Efinix FPGAs. Develop adaptable skills to tackle challenges effectively and gain insights spanning from keyboards to complex servers. What You'll Work On: Engage in our thrilling projects, delving into various facets of our Acceleration framework encompassing AI Acceleration, Software Acceleration, and optimizing peripherals. Gain hands-on experience in Verilog and System Verilog, mastering the fundamentals of these languages. Join Us at Vicharak - Shape the Future of Computing! If you possess an unwavering interest in this field and an insatiable thirst for knowledge, we want to hear from you! Come be part of Vicharak and be at the forefront of molding the future of computing through our groundbreaking FPGA technology. For more insights, visit our website: https://vicharak.in