2715 Verilog Jobs - Page 5

The people are the culture. We encourage a culture of passion for technology solutions that impact businesses. We also make sure that our people pursue their individual passions. Working with us means you get an in-depth understanding of a range of industries and emerging technologies that help us build solutions that are futuristic and impactful. More importantly, the experience of being at MarvyLogic may help you evolve as a person toward enjoying a more fulfilling life. Minimum BE/BS degree in Electrical/Electronics/Computer science required. At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts. Experience in physical layer ASIC architecture, micro-architecture development, design and debug. Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog. Experience with lint, synthesis, CDC, STA, formality, ECO process, tool flows, and scripting. Knowledge in one or more of the following areas, a definite plus: Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer), DSP fundamentals/Filter/FFT design/Datapath design/Error Control Coding, Computer architecture/Processor fundamentals. Preferred Qualifications: Strong knowledge of ASIC design methodologies and flows. Ability to proactively take on responsibilities and competent to work in a start-up environment. Worked with product development companies and having seen at least a couple of tape-outs. Experience with silicon bring-up in the lab and debugging is a definite plus. Experience with FPGA realizations of higher complexity designs. Ability to work with teams spread across geography with excellent communication skills. Responsibilities: Develop key blocks of logic in a next-generation physical layer/mixed signal SOCs. Perform hardware feasibility analysis and come up with a micro-architecture specification helping it map to a high performance, implementable design. Work with verification, DFT, synthesis, circuits, backend implementation teams to realize quality implementation.,

Eximietas Hiring Senior Design Verification Engineers/Leads (PCIE) Experience - 10+ Yrs. Location - Hyderabad Job Description: Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans. Develop and implement comprehensive verification strategies , including test plans, testbenches, and coverage analysis, for both high-speed and low-speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM ). Conduct Gate-level simulations and power-aware verification using tools like Xprop and UPF . Collaborate closely with cross-functional teams, including architects, designers , and pre/post-silicon verification teams , to ensure alignment and seamless integration of verification efforts. Analyze and implement System Verilog assertions and functional coverage (code, toggle, functional) to ensure thorough verification of design functionality. Provide mentorship and technical guidance to junior verification engineers, helping to elevate team performance. Lead and manage a dynamic team of verification engineers, fostering a collaborative and innovative work environment . Ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Demonstrate strong dedication, work ethic, and commitment to meeting project goals and deadlines . Uphold quality standards and implement best test practices , contributing to continuous improvements in verification methodologies. Work with verification tools from Synopsys and Cadence , including VCS and Xsim . Integrate third-party VIPs (Verification IP) from Synopsys and Cadence to enhance verification coverage. Qualifications: 10+ years of hands-on experience in SoC Design Verification . Expertise in verification of high-speed SoCs and various protocols, including I2C/I3C , SPI , UART , GPIO , QSPI , PCIe , Ethernet , CXL , MIPI , DDR , and HBM . Proficiency in System Verilog for verification, including assertions and coverage . Experience with gate-level simulations and power-aware verification using Xprop and UPF . Strong hands-on experience with VCS and Xsim from Synopsys and Cadence . Mentorship experience, providing guidance to junior engineers and managing verification teams. Demonstrated ability to work with cross-functional teams , ensuring effective collaboration and verification signoff. Strong understanding of verification methodologies and ability to contribute to their continuous improvement.

Eximietas Hiring Senior Design Verification Engineers/Leads (PCIE) Experience - 10+ Yrs. Location - Visakhapatnam. Job Description: Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans. Develop and implement comprehensive verification strategies , including test plans, testbenches, and coverage analysis, for both high-speed and low-speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM ). Conduct Gate-level simulations and power-aware verification using tools like Xprop and UPF . Collaborate closely with cross-functional teams, including architects, designers , and pre/post-silicon verification teams , to ensure alignment and seamless integration of verification efforts. Analyze and implement System Verilog assertions and functional coverage (code, toggle, functional) to ensure thorough verification of design functionality. Provide mentorship and technical guidance to junior verification engineers, helping to elevate team performance. Lead and manage a dynamic team of verification engineers, fostering a collaborative and innovative work environment . Ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Demonstrate strong dedication, work ethic, and commitment to meeting project goals and deadlines . Uphold quality standards and implement best test practices , contributing to continuous improvements in verification methodologies. Work with verification tools from Synopsys and Cadence , including VCS and Xsim . Integrate third-party VIPs (Verification IP) from Synopsys and Cadence to enhance verification coverage. Qualifications: 10+ years of hands-on experience in SoC Design Verification . Expertise in verification of high-speed SoCs and various protocols, including I2C/I3C , SPI , UART , GPIO , QSPI , PCIe , Ethernet , CXL , MIPI , DDR , and HBM . Proficiency in System Verilog for verification, including assertions and coverage . Experience with gate-level simulations and power-aware verification using Xprop and UPF . Strong hands-on experience with VCS and Xsim from Synopsys and Cadence . Mentorship experience, providing guidance to junior engineers and managing verification teams. Demonstrated ability to work with cross-functional teams , ensuring effective collaboration and verification signoff. Strong understanding of verification methodologies and ability to contribute to their continuous improvement.

Eximietas Hiring: ASIC SOC RTL Micro Architect Experience: 8+ years Location: Visakhapatnam Job Description: Eximietas Design is seeking an experienced and highly skilled RTL Micro Architect to join our growing team. As a key contributor, you will play a critical role in defining and implementing the microarchitecture of cutting-edge semiconductor designs. You will work on complex RTL design challenges, collaborate with cross-functional teams, and contribute to the delivery of high-performance, power-efficient, and innovative solutions. Key Responsibilities: Define and develop microarchitecture specifications for complex SoC designs. Lead RTL design and implementation using Verilog/System Verilog, ensuring optimal performance, power, and area (PPA). Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution. Perform design trade-off analysis to meet functional, performance, and power requirements. Develop and implement design methodologies to improve efficiency and quality. Mentor and guide junior engineers, fostering a culture of innovation and excellence. Participate in design reviews, provide technical leadership, and ensure adherence to project timelines. Qualifications: 8+ years of hands-on experience in RTL design and microarchitecture development. Strong expertise in RTL design using Verilog/System Verilog and logic synthesis . Proficiency in microarchitecture design for complex SoCs, including pipelining, caching, and memory subsystems . Experience with low-power design techniques (e.g., clock gating, power gating, multi-Vt optimization). Familiarity with advanced process nodes and their specific challenges (e.g., finFET, multi-patterning). Strong scripting skills in Tcl, Python, or Perl for automation and flow development. Excellent problem-solving skills and attention to detail. Strong communication and leadership skills. What We Offer: Opportunity to work on cutting-edge semiconductor designs and innovative technologies. Collaborative and inclusive work environment. Competitive compensation and benefits package. Professional growth and development opportunities. Interested Engineers please share your updated resume: maruthiprasad.e@eximietas.design

Hi All, Greetings' from Eximietas Design....! We are Hiring ASIC SOC RTL Design Engineer/Leads. Job Title: ASIC SOC RTL Design Engineer/Leads ..! Experience: 8+ Years. Location: Visakhapatnam or Bangalore. Job Description: Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a critical role in defining and implementing the microarchitecture of cutting-edge semiconductor designs. You will work on complex RTL design challenges, collaborate with cross-functional teams, and contribute to the delivery of high-performance, power-efficient, and innovative solutions. Key Responsibilities: Define and develop microarchitecture specifications for complex SoC designs. Lead RTL design and implementation using Verilog/SystemVerilog, ensuring optimal performance, power, and area (PPA). Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution. Perform design trade-off analysis to meet functional, performance, and power requirements. Develop and implement design methodologies to improve efficiency and quality. Mentor and guide junior engineers, fostering a culture of innovation and excellence. Participate in design reviews, provide technical leadership, and ensure adherence to project timelines. Qualifications: 8+ years of hands-on experience in RTL design and microarchitecture development. Strong expertise in RTL design using Verilog/SystemVerilog and logic synthesis . Proficiency in microarchitecture design for complex SoCs, including pipelining, caching, and memory subsystems . Experience with low-power design techniques (e.g., clock gating, power gating, multi-Vt optimization). Familiarity with advanced process nodes and their specific challenges (e.g., finFET, multi-patterning). Strong scripting skills in Tcl, Python, or Perl for automation and flow development. Excellent problem-solving skills and attention to detail. Strong communication and leadership skills. What We Offer: Opportunity to work on cutting-edge semiconductor designs and innovative technologies. Collaborative and inclusive work environment. Competitive compensation and benefits package. Professional growth and development opportunities. Interested Engineers please share your updated resume : maruthiprasad.e@eximietas.design

Bangalore, India • Full Time Meta Infrastructure Engineering Hardware Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Design Verification Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Track record of 'first-pass success' in ASIC (Application-Specific Integrated Circuit) development cycles 5+ years of experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification 5+ years experience in IP/sub-system and/or SoC (System on Chip) level verification based on SystemVerilog UVM and OVM (Open Verification Methodology) based methodologies Experience in one or more of the following areas along with functional verification - System Verilog Assertions, Formal, Emulation Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Preferred Qualifications 8+ years of experience in development of UVM based verification environments from scratch Experience in IP, sub-system and SoC level verification using SystemVerilog, UVM Experience with IP or integration verification of high-speed interfaces like AMBA, PCIe (Peripheral Component Interconnect Express), DDR (Double Data Rate), Ethernet Experience with verification of ARM/RISC-V based sub-systems or SoC (Systems on Chip) Experience with Design verification of Data-center applications like Video, Artificial Intelligence/Machine Learning (AI/ML) and Networking designs Experience with revision control systems like Mercurial, Git or SVN Experience working across and building relationships with cross-functional design, model and emulation teams About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Design Verification Engineer (Senior Level - 5+ years’ experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 5+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

We are seeking a Senior R&D Engineers to join our world-class Synthesis team in Noida, which supports a range of EDA products. Does this sound like a good role for you? Senior/Lead R&D Engineer (C/C++, Data structures, Algorithms) Location: Noida Experience: 4yrs to 12yrs Strong hands-on experience in C/C++ based software development . Strong background in Design Patterns, Data Structure, Algorithms, and programming concepts. Familiarity with multi-threaded and distributed code development & ASIC design flow and the EDA tools and methodologies used therein. Good knowledge of Verilog, System Verilog & VHDL HDL Well versed with Software Engineering and development processes Experience of production code development on Unix/Linux platforms. Exposure to developer tools such as gdb, Valgrind Exposure with source code control tool like Perforce. Responsibilities: Candidate will be part of word level Synthesis team (catering to multiple EDA products). Design, develop, troubleshoot the core algorithms. Will be working with local and global teams. Will be working on Synthesis QoR, Performance and logic interference problems It is a pure technical role & drive solutions to complex problem with other team members Please share your updated CV with taufiq@synopsys.com or refer those who would like to explore this opportunity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

Design Verification Engineer (6+ years’ experience)/Limited Walkin interview (Physical Drive) on 23rd of Aug'25, Saturday Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 6+ years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

Design Verification Manager We need an experienced DV lead/manager to verify IP/SoC using System Verilog/UVM Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 7+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded

Job Description Quick learner with strong critical thinking and creative problem-solving skills. Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies. Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA). Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc. Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations. 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips. Familiar with programming languages: C, C++, and/or SystemC. Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus. Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus. Requirement Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. Document on new flows and processes for AMS DV. Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.

Job Description Summary Lead FPGA Engineer will be responsible for leading/executing complex FPGA design projects and solutions. You will work in a global environment with skilled team of engineers creating and improving a state-of-the-art platform for use in every kind of power generation application Job Description Essential Responsibilities Select the FPGA, CPLD family and chip suitable for the application. Develop FPGA design requirements based on system requirements document. Define FPGA interfaces with other circuitry along with hardware design engineer. Do FPGA programming, synthesis and simulation, timing analysis and optimization. Validate system along with the hardware and firmware design engineers to confirm about functionality, reliability, efficiency, compatibility and responsiveness. Work on FPGA-based solutions for interfacing real-time microprocessor systems to high speed Networks and I / O Actively drive design rigor and participate in relevant formal design reviews Contribute to board level reliability analysis and system FMEA Identify opportunities to modify/author DPs Identify cost-out opportunities and make technical proposals Lead/ Participate on teams assigned to address organizational initiatives. Qualifications/Requirements Bachelor / Masters in Electronics Engineering, Electronics & communication, Computer Engineering or equivalent. 8-10 years of experience in FPGA design, digital circuit design, system level analysis, Product Development life cycle including system and Sub-system Design Proven analytical and organizational ability Strong interpersonal and leadership skills Strong oral and written communication skills Effective problem identification and solution skills Desired Characteristics Hands on experience in Verilog, VHDL, FPGA development tools, including design, synthesis, simulation, timing analysis, optimization, packaging and debug Expertise in Signal Integrity and simulations Knowledge about different communication techniques Hands on experience in developing the interfaces between FPGA and other devices like microprocessors, ADCs, transceivers and so on. Strong experience of High-speed digital designs, Proficiency in ECAD suite of tools either from Mentor Graphics or Cadence would be an added advantage. Should have a good understanding of EMI/EMC concepts related to high speed designs and debug issues. Experience working with Industry protocols like MODBUS, FF,CAN, Ethernet Ability to coordinate several projects simultaneously. Experience in Agile methodology. Additional Information Relocation Assistance Provided: Yes

Job Description In your new role you will: Will be part of a team that handles Verification for complex SoCs and close the Verification to the challenging milestones. SoC Verification: Full-chip VR creation as per the chip requirements and UVM/OVM Test benches creation Support in building verification infrastructure at the chip level asper the requirements Capable of handling multiple areas of SoC Verification: RTL, Power Aware and Gate Level Verification Your Profile You are best equipped for this task if you have: Bachelor's - 6 to 7 years’ experience, Master’s - 5 to 6 years’experience Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of SoCs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements well and good knowledge in industry standard protocols is a plus Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Job Description Change the world. Love your job. TI is seeking a candidate for the role of Analog and Mixed Signal Design Verification Engineer. About The Team The Voltage Reference and Supervisors team in the TI-Analog Power Products vertical is engaged in development of cutting age products in the domain of voltage references and supervisor IC’s. The products developed by the team are used in wide variety of end-equipment’s ranging from test and measurement – bench equipment’s like DMMs, DAQ systems, channel cards in ATE, to solar inverters and automotive subsystems for ICE/HEV/EV vehicles. The product mix ranges from highest precision products (ppm grade accuracy) to highest voltage (1000+) semiconductor products. The team in Bangalore, owns all major functions in product development – design, layout, validation, test and program management, giving team members a very unique and overall exposure to product development. Job Responsibilities You will be responsible for owning and driving Design verification for assigned project(s). Work will involve, Engage with Design and System team to understand the overall product functionality, customer use cases and key care bouts. Understand the device specification in detail from the data sheet and come up with a detailed simulation plan with coverage of Electrical and System, break-the-part tests. Simulate the Design with due diligence in accordance to the Simulation plan Have the intuitive ability to corelate the simulation results to the design Document the key observation and with ability to summarize the results. On anomalous behavior observed, perform debug to understand if the behavior is because of limitations of the stimulus, design or any potential settings in the simulation environment Support the Validation and Test team on correlating the setups/stimulus provided during the device testing. Qualifications Knowledge and Skills expected: Good understanding of semiconductor device fundamentals Decent knowledge on analog, power and mixed signal circuit fundamentals. Ability to model blocks/sub-blocks as required using System Verilog, Verilog-A, Verilog-AMS etc. Ability to read and debug RTL code. Have flair for automation with knowledge of Unix and other scripting tools Proficiency in cadence tools and simulator settings to get the best trade off for design accuracy and simulation speed Understanding of DV concepts such as UVM, coverage, randomization Good oral and written communication skills. Ability to convey thoughts with clarity. We value candidates who exhibit depth of understanding of the work they have already done. About Us Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

Job Description Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry. About ASM Auto ASM (Application specific Microcontroller) business powers automotive and industrial MCU across multiple applications. ASM is now working on next generation Automotive MCU platform for all kind of vehicle applications e.g. Traction motor control, Charging, Lighting and Heating control, IC Engine management etc. This platform will churn out multiple differentiated products for Zonal networking in Software defined Vehicles (SDV) and superior real time control for EV Cars. Great opportunity to be part of this grounds up platform development across process nodes, IPs and SoCs. https://www.ti.com/applications/automotive/overview.html Responsibilities Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes: Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics SubSystem/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes. DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines Qualifications Qualifications: 2-5 years of DV experience in SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Skills Experience in one or many of the following: C based SOC DV, scripting (Python/Perl/Shell) knowledge, DV flow ownership for functional/Formal verification, UVM/System Verilog deep understanding, AMS/GLS/PAGLS/CPF/UPF based verification, Post silicon verification etc. Strong in digital design fundamentals, computer organization & architectures and bus protocols Excellent debugging skills with Verilog/VHDL designs Thorough knowledge in one or many of the standard protocols. Ex: AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray etc Work experience on C based environment with ARM/DSP multi-processor-based systems including the power aware simulations is a big plus Good problem-solving skills Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Exposure to CDC DV, Post silicon verification and functional safety is an added advantage Effective communication skills to interact seamlessly with all stakeholders Must be highly focused and remain committed to obtaining closure on project goals About Us Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

Staff / SR. Staff Digital Design Engineer, Interface IP Description & Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An enthusiastic and detail-oriented ASIC Digital Design Engineer with a passion for cutting-edge technology and a penchant for solving complex problems. You thrive in a collaborative environment and are adept at translating high-level requirements into robust and efficient designs. Your expertise, coupled with your strong understanding of digital design and verification methodologies, makes you an invaluable asset to any project. You are proactive, with excellent communication skills that enable you to work effectively with cross-functional teams. Your ability to adapt quickly to new challenges and technologies ensures that you remain at the forefront of industry advancements. What You’ll Be Doing: Designing and verifying digital IP for ASICs, focusing on interface IPs. Performing RTL coding and simulation to optimize design performance and efficiency. Collaborating with cross-functional teams to ensure thorough testing and validation of designs.. Conducting design and verification reviews and providing constructive feedback to improve overall quality and functionality. Debugging and resolving complex design and verification issues. Documenting design specifications, test plans, and verification reports. The Impact You Will Have: Contributing to the successful delivery of high-performance IPs. Enhancing the reliability and performance of Synopsys products through rigorous design and verification. Driving innovation by developing cutting-edge solutions for interface IP. Strengthening Synopsys’ reputation as a leader in the semiconductor industry. Improving the efficiency and effectiveness of the design and verification process. Supporting the continuous improvement of design methodologies and best practices. What You’ll Need: Proficiency in digital design and verification methodologies. Experience with RTL coding using Verilog or SystemVerilog. Strong understanding of digital design principles, including timing analysis and optimization. Expertise in using advanced verification techniques, including UVM. Familiarity with scripting languages such as Python or Perl for automation. Who You Are: An analytical thinker with a keen eye for detail. A proactive problem-solver who can navigate complex challenges. An excellent communicator who can articulate technical concepts to diverse audiences. A collaborative team player who thrives in a dynamic environment. A continuous learner who stays updated with industry trends and advancements. A results-driven professional committed to delivering high-quality work. The Team You’ll Be A Part Of: You will join a dedicated team of engineers focused on the design and verification of high-performance digital IPs. Our team is committed to innovation, quality, and excellence, working collaboratively to push the boundaries of technology. We value continuous learning and professional growth, providing ample opportunities for development and advancement.

PROXELERA Hiring an experienced Lead SoC / NoC Verification Engineer 10+yrs of experience in Bangalore to drive the verification of high-performance SoC / NoC Interconnect Architectures This role demands a blend of technical depth, leadership and a strong strategic mindset Title: Lead SoC / NoC Verification Engineer Bangalore, India Responsibilities Lead verification projects for complex SoC and NoC Subsystems. Develop scalable and reusable System Verilog / UVM-based environments Define and implement test plans for functional coverage performance and corner-case analysis Collaborate with design teams to debug and resolve challenging logic and protocol-level issues Work with high-speed interconnects and protocols such as AXI, CHI, PCIe, Ethernet, CXL, and UCIe Drive verification strategy including automation regression setup and coverage closure Mentor junior engineers and guide cross-functional technical discussions. ✅ Preferred Experience Deep hands-on expertise in SoC/NoC-level verification Strong debug skills using waveform tools and log analysis Exposure to power/performance optimization and metrics-driven verification Proven experience working in complex testbench architectures Why Join a Leading Semiconductor Product Company? 💡 Broadest Portfolio of AI Solutions From CPUs and GPUs to adaptive computing platforms, offers the industry’s most complete suite of AI-enabling technologies-optimized for edge cloud and endpoint workloads 🌐 Open Ecosystem Philosophy Their commitment to open standards and strategic co-innovation fosters maximum flexibility long-term scalability and compatibility across the global tech landscape 🚀 Proven Innovation Leadership With breakthroughs like chiplet architecture 3D stacking and AI accelerators the company consistently delivers best-in-class TCO energy efficiency and performance leadership across industries If you’re passionate about design excellence and eager to work on cutting-edge semiconductor technologies, send your resume to girish.nidyamale@proxelera.com DM / call +91 96329 00829

Qualcomm India Private Limited is seeking talented engineers for CPU RTL development targeted at high-performance, low-power devices. As a CPU Micro-architecture and RTL Design Engineer, you will collaborate with chip architects to conceptualize the micro-architecture and contribute to architecture/product definition early in the product life-cycle. Your responsibilities will include performance exploration, microarchitecture development and specification, RTL ownership to achieve power, performance, area, and timing goals, functional verification support, performance verification support, and design delivery in coordination with a multi-functional engineering team. To excel in this role, you should have a thorough understanding of microprocessor architecture, expertise in areas like instruction fetch and decode, Verilog/VHDL knowledge, logic design principles, low power microarchitecture techniques, high-performance techniques, and experience with scripting languages such as Perl or Python. Minimum qualifications include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of Hardware Engineering experience. Preferred qualifications involve a Master's degree in a relevant field, 8+ years of Hardware Engineering experience, and experience in circuit design and hardware measurement instruments. Your principal duties will involve leveraging advanced hardware knowledge to plan, optimize, verify, and test critical electronic systems, integrate complex features into hardware designs, collaborate with cross-functional teams, evaluate and develop novel manufacturing solutions, and write detailed technical documentation for complex hardware projects. As a qualified candidate, you are expected to work independently with minimal supervision, provide guidance to team members, make significant decisions affecting work beyond immediate groups, possess strong communication skills, and have a moderate influence on key organizational decisions. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, please contact disability-accommodations@qualcomm.com. Additionally, Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to confidentiality and protection of company information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm, and unsolicited submissions from staffing and recruiting agencies are not accepted. For more information about this role, please reach out to Qualcomm Careers directly.,

As an ASIC Verification Engineer at our game-changing AI solutions company, you will be responsible for developing verification environments for modules, subsystems, top level, and FPGA. You will build models, checkers, and random test frameworks using SystemVerilog and UVM. Additionally, you will participate in Low power analysis (UPF), power estimation, and C modeling. Your role will also involve performing lint, CDC, code coverage, and functional coverage, as well as formal verification of modules using SVA assertions. To excel in this role, you should have experience in verifying complex subsystems and ASICs. You should be adept at building scalable verification environments from scratch and proficient in Verilog, UVM, EDA tools, scripting, automation, build, and regression systems. Exposure to FPGA emulation platforms, silicon bringup, and board debug will be beneficial for this position. A degree in BTech/MTech in EE/CS with any level of experience is required to be considered for this opportunity. If you are passionate about pushing the boundaries of AI technology and want to be a part of the edge AI revolution, we look forward to hearing from you. Please reach out to us at +91-9071106778 to explore this exciting opportunity further.,

At Atos, we are a global leader in digital transformation, employing around 78,000 individuals and generating an annual revenue of approximately 10 billion. As the top cybersecurity, cloud, and high-performance computing provider in Europe, we offer customized end-to-end solutions to various industries across 68 countries. We are at the forefront of decarbonization services and products, dedicated to providing our clients with secure and sustainable digital solutions. Atos operates as a SE (Societas Europaea) and is listed on Euronext Paris. Our mission at Atos is to shape the future of the information space. Through our expertise and services, we facilitate the advancement of knowledge, education, and research in a diverse cultural context, fostering scientific and technological excellence. Globally, we empower our customers, employees, and broader communities to thrive and progress sustainably within a secure information environment. We are currently seeking a skilled FPGA Design Engineer to join our team in Bangalore (Whitefield) with a minimum of 3 years of experience. The ideal candidate should hold a Bachelor's Degree (BE/BTech) or a Master's Degree (ME/MTech) in Electronics. Key Responsibilities: - Design FPGAs for Server Motherboards based on specified requirements - Create detailed design documentation for FPGA implementation - Develop test benches and conduct verification processes - Perform on-board validation of FPGAs Qualifications and Experience: - Educational background in BE/BTech/ME/MTech in Electronics - Minimum of 3 years of experience in FPGA development - Proficiency in FPGA design using Verilog/VHDL - Hands-on experience in FPGA design implementation and verification - Expertise in timing closure and setting constraints - Familiarity with Xilinx, Altera/Intel, and Lattice tools - Strong problem-solving and debugging skills - Ability to collaborate effectively with global teams across different geographies At Atos, diversity and inclusion are integral to our organizational culture. We are committed to fostering a fair work environment for all individuals. Additionally, our company is recognized for its leadership in Environment, Social, and Governance (ESG) criteria. Learn more about our Corporate Social Responsibility (CSR) initiatives and our dedication to sustainability. If you are looking to shape your future in a dynamic and inclusive work environment, consider joining Atos. Choose a career that aligns with your values and aspirations.,

You will be responsible for designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. This includes designing and implementing RTL for DFT IP, including POST and IST. Additionally, you will be developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Your role will also involve owning, maintaining, extending, and enhancing existing DFT IP like LBIST. At Cadence, we are focused on hiring and developing leaders and innovators who are passionate about making an impact on the world of technology. Join us in our mission to solve challenges that others cannot.,

Principal / Staff Design Verification Engineer Bangalore Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they're looking for passionate individuals to join a seasoned and dynamic team. Positions Available in Bengaluru, India/fully onsite Principal Design Verification engineer Responsibilities​: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc.​ Qualifications and Preferred Skills​ BS, MS in Electrical Engineering, Computer Engineering or Computer Science 6-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs Experience with formal verification techniques, emulation platforms is a plus Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

AI Centre Ethernet Switching Architect India-remote. person could be based anywhere in India - Remote work will be considered for exceptional profiles Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore AI Centre Ethernet Switching Architect Position Overview We are seeking a top-notch specialist Architect with over 20 years of experience to join our team in designing and developing Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet/TCP/IP protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, UALink, Ultra Ethernet with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Define and develop the architecture of AI Datacentre Switch Fabric from ground up Performance Modelling and optimization of latency, throughput and power efficiency of switch fabric Decompose the architecture into sub blocks for implementation by design team Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control, packet spraying Apply knowledge of InfiniBand/Ultra Ethernet, NVLink/UALink, or similar protocols for feature implementation. Understanding/experience of IOS/Junos or equivalent software platform Use P4 or related languages for programmable packet processing. Working with design, software, verification team for complete product solutions Documentation of architecture and stay updated on AI networking trends. Required Qualifications Education: MS/PhD in Electrical/Electronic Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Soft Skills: Strong problem-solving, communication, and teamwork skills. Position Overview Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Wafer Space is looking for expert DFT engineers for development, support, maintenance, Implementation and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills And Experience- 3 - 7 year's experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation