2715 Verilog Jobs - Page 4

Job Description We are hiring an RTL Engineer – Global Library with strong expertise in RTL design and library development. The candidate will be responsible for RTL coding, integration, and validation of reusable libraries, ensuring high-quality design standards. Key Responsibilities Develop and maintain Global RTL libraries . Work on RTL coding, integration, and validation. Collaborate with design and verification teams for smooth adoption. Ensure reusability and optimization of libraries across projects. Required Skills Strong experience in RTL design . Proficiency in Verilog/SystemVerilog . Hands-on experience with EDA tools & synthesis . Good understanding of library development and usage in VLSI design. Compensation: Based on experience Experience: 4+ Years Job Type: Full-time Ability to commute/relocate: Bangalore, Karnataka: Reliably commute or planning to relocate before starting work (Preferred) Work Location: In person Application Deadline: 23/08/2025

RGreetings!!!!! We are looking for a Engineer / Sr. Engineer _ FPGA Design _ Bangalore location for a leading Indian multinational in Electronics System Design & Manufacturing. Job Responsibilities: High-speed digital architecture design (FPGA based) FPGA design using Xilinx devices & tools (Vivado/ISE) Implementing DSP algorithms on FPGA Hands-on with protocols: JESD204, LVDS, Aurora, UART, SPI, I2C Perform Static Timing Analysis (STA), synthesis, placement, routing & floorplanning Apply design constraints for timing closure Develop test benches for verification & validation Collaborate with cross-functional teams for new product development Requirements: 4 to 8 years of FPGA design experience Strong in RTL to FPGA implementation & onboard testing Experience in DSP algorithm-to-hardware conversion Good knowledge of verification, validation & debugging methods If your interested share with the below details to uma@bvrpc.com Please share your updated resume along with: Current CTC Expected CTC Notice Period

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

System Design & Architecture : Lead architectural planning and design of software systems prioritizing scalability, reliability, and maintainability. Development & Coding : Write clean, efficient, and well-documented code. Implement robust testing, including unit and integration tests. Project Leadership : Drive projects from concept to delivery. Break down tasks, estimate effort, track milestones, and manage technical risk in collaboration with PMs and stakeholders.

Role Description Share point developer with good experience in Pages and Workflow. Excellent Communication skills. Offshore resource who specializes in Sharepoint (i.e. Pages, workflow) development, etc.). 5-6 yrs of experience.

Job Description We are looking for an experienced Design Verification Engineer to join our team and contribute to the verification of complex SoC/ASIC designs. The ideal candidate will have strong expertise in verification methodologies, testbench development, and debugging. Key Responsibilities: Develop and implement verification plans, environments, and testbenches using SystemVerilog/UVM. Write and execute test cases for functional, regression, and coverage-driven verification. Perform debugging and root cause analysis for design and verification issues. Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables. Analyze functional coverage metrics and enhance test suites for improved quality. Work on assertion-based and formal verification techniques where applicable. Contribute to automation and scripting to streamline verification flows.

Education: Bachelors degree (BE/B.Tech)orMasters degree (ME/M.Tech) Roles & Responsibilities: Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team. Write and perform the test plan in close cooperation with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog C++. Write, maintain and publish the verification specification. Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Produce a maintainable and reusable code across projects Required Skills and Experience Curious, demanding and rigorous. Mastering object oriented programming. Knowledge of UVM verification methodology (or equivalent) and SystemVerilog SystemC hardware verification languages Knowledge of Constraint-Random Coverage-Driven verification environments development in SystemVerilog C ++ (drivers monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp SVA) Knowledge of simulation tools and coverage database visualization tools Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints. Our Offering: Competitive salary package Leave Policies: 10 Days of Public Holiday (Includes 2 days optional) & 22 days of Earned Leave (EL) & 11 days for sick or caregiving leave. Benefit Plans (Insurance) Medical & Life & Accidental & EDLI

Job Overview Experience: 3 – 15 years Responsibilities Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks—defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills And Experience Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Job Title: Design Verification Engineer Experience: 10+ Company: Avecas Job Overview: We are seeking motivated Design Verification Engineers to join our VLSI team. The role involves verifying complex digital designs at block and SoC level using advanced methodologies to ensure functional correctness, quality, and performance. Key Responsibilities: Develop and execute test plans, testbenches, and verification environments . Work on SystemVerilog/UVM-based verification . Create and run directed, constrained-random, and regression tests . Debug and resolve design/verification issues using EDA tools. Collaborate with RTL design, architecture, and physical design teams. Document verification results and maintain coverage metrics. Required Skills: Strong knowledge of Digital Design and Verilog/SystemVerilog . Understanding of functional verification methodologies (UVM/OVM). Hands-on experience with EDA tools (simulation, debugging, coverage analysis). Familiarity with scripting languages (Python, Perl, TCL, Shell) is a plus. Good problem-solving, debugging, and communication skills. Nice to Have (for experienced candidates): Exposure to SoC-level verification . Knowledge of low power verification, CDC, or formal verification . Experience in industry-standard simulators and verification IPs . Why Join Us? ✅ Opportunity to work on cutting-edge SoC/ASIC projects . ✅ Collaborative and learning-driven environment. ✅ Growth opportunities in the VLSI design & verification domain.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications. What You Can Expect In this role based in Hyderabad, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What We're Looking For Bachelor’s Degree in Electronics/Electrical Engineering or related fields and have 5-8 years of related professional experience OR a Master’s degree and/or PhD in Electronics/Electrical Engineering or related fields with 4-7 Years of related professional experience. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis. Good understanding of standard Synthesis to GDS flows and methodology. Good scripting skills in languages such as Perl, tcl, and Python. Good understanding of digital logic and computer architecture. Hands-on experience in advanced technology nodes upto 2nm. Strong hands-on experience in blocks/subsystem P&R implementation using Cadence Innovus and Synopsys FC. Good experience in block level signoff power, timing, PV closure & debugging skills. Knowledge of Verilog/VHDL. Good communication skills and self-discipline contributing in a team environment. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities MTS (Development and Validation) Responsible for deep understanding, architecting and implementing of complex System Validations frameworks involving custom devices driver for hardware and firmware solutions like Storage Devices like SSD Responsible for thinking complex field scenarios and implementing algorithms to simulate them. Skills Must have 7-15 yrs exp Experience and Mandatory knowledge in PCIe, NVME/Storage devices and drivers. Experience in terms of device drivers of PCI devices like ethernet devices. Experience in C/C++ programming Experience in some System-Level Validation frameworks along with automation where we are validating different hardware and firmware components from host on top of device drivers. Past experience of grey box testing software Experience with development of complex software code base , debugging and fixing the issues Experience in Linux Operating system concepts and Qemu Experience with Multi-threaded software development in Linux environment Knowledge of core computer science concepts such as object-oriented design, algorithm design, data structures, problem solving, and complexity analysis Experience in Software programming for FPGAs is an advantage Nice to have Excellent interpersonal, written and verbal communication skills Excellent communication, problem solving and analytical skills Location - pune,mumbai,chennai,banagalore

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 6+ years of experience. Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash. Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: RTL coding.Experience: 5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: RTL coding.Experience: 3-5 Years.

We are looking for skilled DFT Engineers with hands-on experience in RTL coding, scan insertion, ATPG, and coverage analysis to join our semiconductor engineering team. Key Responsibilities: Perform scan insertion, JTAG, ATPG DRC, and coverage analysis. Debug simulation with timing/SDF and root cause failures. Work on LBIST and Mixed Signal Radar ICs. Collaborate closely with design and verification teams. Ensure quality deliverables with proactive and detail-oriented work. Key Skills: Verilog / VHDL RTL coding Mentor DfT Tools, Cadence Tools Scan Insertion, JTAG, ATPG, Coverage Analysis LBIST, Mixed Signal Radar ICs (Preferred) Simulation Debug with Timing/SDF Soft Skills: Strong interpersonal and communication skills Proactive, collaborative, and self-motivated Ability to work independently and in a team

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Required Skills and Experience : Bachelor’s or Master’s Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field. The role of Senior DFT engineer require 5+ years of industry experience with shown ability in DFT of highly sophisticated SOCs : Core skills include Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG (IEEE1149.1 & IEEE1687), Fault Simulation, ATPG Fault models(SAF, TDF, SDD, PDT etc), SDF annotated gate level verification, Scan and Memory Diagnosis. Must have experience with Siemens, Synopsys and/or Cadence Cad tools. Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python. Responsibilities - Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level. Generate and validate ATPG patterns using simulations. Shall Validate the DFT implementation using RTL and Gate level simulation. Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation. Support the Silicon bring up activities to guarantee the highest stability of the test patterns/program. Chip in to the overall DFT methodology development. Nice to have Skills/Experience :- Shall have Knowledge of IEEE 1149.6, 1500 and 1838. Good experience on Hierarchical Scan implementations with core wrapping concepts Experience in handling multi-clock domains and low power design implementation. Knowledge/Experience on SSN, 2.5D or 3D IC DFT implementation. Communicate effusively with multi-functional functional teams in different geographies and time Zones. Time management and multi-tasking skills. Job Location: You will be joining part of growing team in Hyderabad About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Job Requirements Job Title: Senior Design Verification Engineer We are currently seeking a Senior Design Verification Engineer to join our team on a temporary basis. As a key member of our engineering team, you will be responsible for verifying and validating complex digital designs to ensure they meet the highest quality standards. Key Responsibilities: Develop and execute verification plans for digital designs Write test benches and test cases to verify functionality Collaborate with design engineers to identify and resolve issues Analyze and debug failures to improve design quality Stay current on industry trends and best practices in design verification Qualifications: Bachelor's degree in Electrical Engineering or related field Proven experience in design verification of digital designs Proficiency in Verilog/SystemVerilog and UVM methodology Strong problem-solving skills and attention to detail Excellent communication and teamwork abilities If you are a talented Design Verification Engineer looking to make an impact in a dynamic and innovative environment, we would love to hear from you. Apply now to join our team!

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements Preferred Experience Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts - Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. Academic Credentials Bachelors or Masters degree in computer engineering/Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Design Verification: SV/UVM Test Bentch Developement Any Protocols: PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 6+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Physical Design: •In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. - Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Floor Planning/Innovus/Fusion Compiler Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. • Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. •Well versed with timing constraints, STA and timing closure. •Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. •Should have experience on programming in Tcl/Tk/Perl • Well versed with timing constraints, STA and timing closure. ASIC RTL Design: • 6+ years experience in RTL, Asic Coding, Design, IP Design, SOC Development, Lint, CDC • PCIe/DDR/Ethernet - Any One • I2C,UART/SPI - Any One • Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One • Scripting languages like Make flow, Perl ,shell, python - Any One DFT Engineer: Interface with ASIC design teams to ensure DFT design rules and coverages are met. Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Analog Circuit Design Lead: 1. 6+ years of Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization. 2. Must have led the entire Analog IP development cycle and team. 3. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. 4. Analog/custom layout design in advanced CMOS process. 5. Ability to understand design constraints and implement high-quality layouts. 6. Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...). 7. Hands-on experience on lower FINFET technology nodes and design/PPA trade-offs.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Semiconductor Integration. Experience: 3-5 Years.

Minimum qualifications: Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience. 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture. Experience in ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master’s degree in Electrical/Computer Engineering. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Experience with methodologies for low power estimation, timing closure, synthesis. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of our platform IP team, you will be a part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis to specify and deliver RTL. You will solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance and power. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. Perform RTL development (SystemVerilog), debug functional/performance simulations. Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Company Description Hughes Systique Corporation (HSC) is a multinational company with headquarters in Rockville, Maryland, and Delhi-NCR, India. The company is CMMi Level 5, ISO 9001:2015, ISO 27001:2013, and PCMMi Level 5 certified, specializing in digital solutions and services. HSC has research and development centers in Gurgaon and Bengaluru, India, providing innovative solutions in Networking, AI & ML, Retail, Automotive, IoT, Blockchain, and Security. Role Description This is a full-time hybrid role for an FPGA Developer located in Gurgaon with the flexibility for some work from home. The FPGA Developer will be responsible for designing and implementing FPGA-based solutions, collaborating with cross-functional teams, testing and debugging FPGA designs, and optimizing performance. The role will involve working on cutting-edge technologies to support the digital transformation journey of clients. Qualifications Experience in FPGA design and implementation Knowledge of digital signal processing and communication systems Proficiency in Verilog, VHDL, and FPGA development tools Strong problem-solving and analytical skills Ability to work collaboratively in a team environment Experience with Xilinx or Altera FPGAs is a plus Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Xona is the navigational intelligence company bringing real-time, centimeter-level certainty to any device, anywhere on Earth. With Pulsar – the world’s most advanced PNT satellite infrastructure in Low Earth Orbit – Xona will offer a future-proof, backwards-compatible global positioning system optimized for absolute precision, superior power, and robust protection. We are seeking a mid-level FPGA Engineer to join our team working on high-reliability digital systems for space-based navigation payloads. In this role, you’ll contribute to the design, implementation, and testing of FPGA logic for real-time, mission-critical applications. You’ll work closely with hardware and systems teams to help bring our next-generation payloads from concept to flight. What You’ll Do Develop, implement, and verify RTL designs for Xilinx FPGAs (e.g., RFSoC, Zynq Ultrascale+) Build and maintain digital processing pipelines, control logic, and data interfaces Support hardware bring-up and system integration on custom satellite payloads Design for fault tolerance and space reliability, including SEU mitigation and system monitoring Collaborate with systems, hardware, and software engineers to define and validate FPGA requirements Participate in lab testing, simulation, and design reviews Document designs, test plans, and development processes in a structured, reviewable format Desired Qualifications Experience working with Xilinx Zynq or RFSoC devices Exposure to space system development, including SEU mitigation techniques and fault-tolerant design Familiarity with high-speed interfaces, memory controllers, or custom peripheral integration Scripting experience (e.g., Python or TCL) for automating test and build processes Experience collaborating on multi-disciplinary hardware/software projects Understanding of space qualification and hardware validation processes is a plus Requirements Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field 3–5 years of professional FPGA design experience using Verilog, VHDL, or SystemVerilog Strong experience with FPGA development flows, including Vivado or similar tools Proficiency in simulation, verification, and hardware debugging techniques Familiarity with on-chip interfaces such as AXI, AXI-Stream, and clock domain crossing Hands-on experience bringing up FPGA designs in a lab environment Comfortable working in a Linux development environment with version control tools like Git Must be able to work full-time onsite in Burlingame, California To comply with U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the United States (i.e. Green Card holder), or other protected individual as defined by 8 U.S.C. 1324b(a)(3). We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.

Technical Skills Required/ Mandatory: 1. B. Tech or M Tech in ECE or CSE or equivalent field & Minimum 3 years of relevant experience in Embedded Hardware Design. 2. Proficiency in electronic circuit design and analysis. 3. Design Analysis, Component selection and Analysis. 4. Expertise in schematic capture and PCB layout tools (e.g., Cadence, Altium). 5. Strong knowledge of digital and analog electronics. 6. Knowledge of high-speed PCB design techniques. Also, Multilayer PCBs and FPGA design. 7. Understanding of signal integrity and power integrity principles. 8. Test the prototypes and debug the issues. 9. Familiarity with microcontroller architectures and programming languages. 10. Competence in simulation and modeling tools (e.g., SPICE, MATLAB). 11. Proficiency in using lab equipment for testing and characterization. 12. Understanding of electromagnetic compatibility (EMC) and electromagnetic interference (EMI) considerations. 13. Knowledge of industry-standard communication protocols (e.g., UART, SPI, I2C, RS422, RS232, Parallel Interface and Ethernet 10/100 mbps). 14. Expertise in power supply design and regulation. 15. Proficiency in using hardware debugging tools (e.g., oscilloscope, logic analyzer). 16. Understanding of embedded systems and firmware development. 17. Knowledge of thermal management techniques. 18. Experience with design for manufacturing (DFM) and design for testability (DFT). 19. Understanding of reliability and failure analysis. 20. Knowledge of regulatory compliance requirements (e.g., FCC, CE). 21. Hardware Documentation. Optional Skills Required 1. Experience in Defense and Aerospace Industry 2. Hands-on knowledge in Simulation Tools like Hyperlynx, Ansys SIWAVE, HFSS or Cadence Sigrity. 3. Experience with FPGA and CPLD programming is an advantage. 4. Competence in hardware description languages (e.g., VHDL, Verilog) is a plus. 5. Familiarity with RF and wireless communication principles

Xona is the navigational intelligence company bringing real-time, centimeter-level certainty to any device, anywhere on Earth. With Pulsar – the world’s most advanced PNT satellite infrastructure in Low Earth Orbit – Xona will offer a future-proof, backwards-compatible global positioning system optimized for absolute precision, superior power, and robust protection. We’re seeking a hands-on Sr. FPGA Engineer to join our team and help design the next generation of space-based navigation payloads. You'll work on cutting-edge signal processing systems, secure hardware modules, and high-reliability designs that fly in orbit. If you thrive in a collaborative, fast-paced environment and are excited by the challenge of developing space-qualified digital systems, we want to hear from you. What You'll Do Architect and implement RTL for Xilinx RFSoC and other space-qualified FPGAs. Design high-performance DSP and signal generation modules for navigation waveforms (e.g., PRN code generation, mixers, modulators). Develop secure hardware blocks (e.g., SHA-256, HMAC) for authentication and anti-spoofing. Build robust data pipelines to move and process signal streams in real-time. Design with space in mind: mitigate single event upsets (SEUs), implement fault detection/correction, and optimize for radiation-prone environments. Work closely with cross functional teams to bring up payload functionality on actual satellite hardware. Simulate, verify, and test your designs rigorously - then see them fly. Desired Qualifications Experience designing for space: SEU mitigation, TMR, scrubbing, or rad-hard flows. GNSS or navigation signal processing expertise (GPS, Galileo, etc.). Crypto hardware design (e.g., SHA-2, HMAC, AES) and experience with secure communication protocols. Familiarity with JESD204B/C, high-speed serial I/O, or RF front-end interfacing. Embedded software experience on ARM (e.g., for control/config of FPGA fabric). Python or TCL scripting for test automation and build flows. Knowledge of space qualification processes, radiation testing, or flight hardware integration, with preference for strong hardware-in-the-loop devops practices. C/C++ programming experience. Experience with digital generation of high performance RF signals. Requirements Bachelor’s or Master’s degree in Electrical or Computer Engineering (or similar). 3+ years of FPGA development experience using Verilog, VHDL, or SystemVerilog. Experience with HDL simulation and verification. Proven experience with AMD/Xilinx platforms-ideally RFSoC or Zynq Ultrascale+ - and their embedded PL+PS architectures. Solid background in DSP fundamentals and real-time signal processing in hardware. Strong grasp of on-chip dataflow, clock domain crossing, and AXI/AXI-Stream buses. Comfortable using Vivado, Riviera Pro, and Synplify. Proven track record of developing in a collaborative environment, including familiarity with git/gitlab and strong documentation discipline. Full-time, onsite in Burlingame, California (this role is not remote or hybrid) To comply with U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the United States (i.e. Green Card holder), or other protected individual as defined by 8 U.S.C. 1324b(a)(3). We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.