662 Systemverilog Jobs - Page 5

As an experienced Verification Engineer with a minimum of 5 years of experience, your primary responsibility will be to lead the verification of DDR memory controller and PHY designs in compliance with DDR standards like DDR3, DDR4, DDR5, and other memory interface protocols. You will be required to develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM, and other industry-standard methodologies. Ensuring protocol compliance is crucial, which includes validating command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Your role will involve creating detailed verification plans based on DDR specifications and requirements, focusing on corner cases, timing, and protocol validation for full coverage. Running simulations, debugging issues using tools like Questa, VCS, or ModelSim, and applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage will be part of your daily tasks. You will set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues. Achieving high functional and protocol coverage is vital, ensuring that timing constraints, corner cases, and failure scenarios are thoroughly verified. Implementing formal verification techniques to validate critical components of the DDR design, ensuring correctness in timing and data flow, and verifying crucial operations will also be part of your responsibilities. This position requires a Bachelor's or Master's degree in ECE/EEE or VLSI/Electronics from a reputable institution. The position is based in Bangalore/Hyderabad.,

As the Lead Verification Engineer at a cutting-edge storage startup in Silicon Valley, you will be responsible for tackling IP and SoC level verification challenges within a Multi-core, complex, high-performance ASIC environment. Your role will involve understanding internal requirements and complexities of the SOC, designing verification methodologies, environments, and test plans, and collaborating with the design team to ensure high-quality verification for first-pass success of the SoC. Located in Bangalore, KA, India, you should hold a BA/BS degree in Electrical/Electronics Engineering with over 10 years of practical experience. Strong fundamentals in digital ASIC design and verification, expertise in ARM cores and related infrastructure, familiarity with AMBA bus protocols, and experience with Verilog, SystemVerilog, UVM, and other verification tools are essential. Knowledge of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, and UART is desirable, along with an understanding of IP designs and verification requirements. Your responsibilities will include defining and developing verification methodologies and test plans based on functional coverage, project management, contributing to IP and SoC verification, collaborating with the design team for design quality improvement, mentoring team members, and establishing processes for verification and quality improvements. Additionally, you will be involved in Gate Level Simulations (GLS), emulation, FPGA-based, and Post Si validation. To excel in this role, you must possess excellent communication and leadership skills to lead a team of verification engineers effectively. Your ability to review test plans, verification tests, and coverage for team members, as well as your strong test creation, debugging capabilities, and functional coverage understanding, will be critical for the success of the projects.,

Design Verification Engineer II Bangalore, Karnataka, India + 2 more locations Date posted Aug 07, 2025 Job number 1857295 Work site Up to 50% work from home Travel 0-25 % Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AI Silicon Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Design Verification Engineer to join the team. #SCHIE Qualifications Qualifications 3–7 years of experience in IP/SoC verification using SystemVerilog and UVM. Strong understanding of digital design fundamentals and verification methodologies. Familiarity with coverage-driven verification and assertion-based verification (SVA). Excellent problem-solving and communication skills. Additional or Preferred Qualifications : Familiarity with writing assertions and formal verification. Knowledge of networking protocols, such as RDMA and Ethernet. Experience with scripting languages, including Python or Perl. Interest in or hands-on experience with deploying AI solutions. Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Responsibilities The AISiE silicon team is seeking a qualified and motivated computer or electrical engineer to contribute to the development of high-quality designs. The team is responsible for producing advanced, custom IP and SoC designs that achieve complex, high-performance functions with exceptional efficiency. In this role you will: Own verification of IP blocks or subsystems from planning through sign-off. Develop and maintain UVM-based testbenches, scoreboards, monitors, and checkers. Write and execute test plans, develop functional coverage models, and drive coverage closure. Debug RTL and testbench issues using industry-standard tools (e.g., Verdi). Collaborate with design, architecture, and post-silicon teams to ensure verification completeness. Contribute to tool and methodology improvements to enhance verification productivity. Participate in code reviews and provide mentorship to junior engineers. Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience in design and development of Security or Audio blocks. Experience with a scripting language like Perl or Python. Experience with DSI2 or MIPI C/D Phy. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Collaborate with architects and develop microarchitecture. Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks. Participate in test planning and coverage analysis. Develop RTL implementations that meet engaged power, performance and area goals. Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up. Create tools/scripts to automate tasks and track progress. Work with multi-disciplined and multi-site teams in Architecture, RTL design, verification, DFT and Partner Domains. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Qualcomm India Private Limited is looking for a skilled individual to join their Engineering Group, specifically focusing on Hardware Engineering. As a member of Qualcomm, you will be part of a team of inventors who have paved the way for 5G technology, leading to a new era of connectivity and endless possibilities that will revolutionize industries, generate employment opportunities, and improve lives. This is just the beginning of the Invention Age, and your expertise is crucial in turning 5G's potential into groundbreaking technologies and products. At Qualcomm CDMA Technologies (QCT), a prominent player in Multimedia integrated circuits, software, and systems for wireless consumer devices, including Smartphones, Netbooks, and E-readers, you will be involved in developing cutting-edge technologies to enhance mobile devices across various domains such as 2D and 3D graphics, audio/video, display, and architecture. Your role will encompass the design and implementation of leading-edge graphics processors, focusing on areas like 2D and 3D graphics, streaming processors, high-speed IO interfaces, and bus protocols. You will be responsible for the architecture and micro-architecture design of the ASIC, RTL design and synthesis, as well as logic and timing verification. The successful candidate will work on specifying and designing digital blocks in the Multimedia Graphics team to be integrated into a wide range of devices. Collaboration and active support for diversity within the team and the company are expected from all Qualcomm employees. **Minimum Qualifications:** - Bachelor's degree in Science, Engineering, or a related field - Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume production - Experience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and design-for-test (DFT) - Knowledge of Computer Architecture, Computer Arithmetic, C/C++ programming languages is desired - Exposure to DX9~12 level graphics HW development is an advantage - Strong communication skills and a collaborative mindset - Required: Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field. - Preferred: Master's degree in Computer Science, Electrical Engineering, Information Systems, or related field. **Additional Requirements:** - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 6+ years of Hardware Engineering or related work experience - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 5+ years of Hardware Engineering or related work experience - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of Hardware Engineering or related work experience Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities throughout the hiring process. Employees are expected to adhere to all applicable policies and procedures, including those related to confidentiality and security protocols. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. This job posting is intended for individuals seeking direct employment with Qualcomm. For more information about this role, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation teams for pre/post Silicon debug is expected, and hands-on experience in Low power design is preferable. Additionally, experience in Synthesis and understanding of timing concepts for ASIC is essential. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in the relevant fields with 2+ years of experience or a PhD with 1+ year of experience would also be considered. Qualcomm is an equal opportunity employer committed to providing accessibility to individuals with disabilities throughout the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not bear responsibility for any fees related to such submissions. For more information about this role, please contact Qualcomm Careers.,

At Cadence, we are looking for a dedicated individual to join our team as a Training Engineer. In this role, you will collaborate with product engineers, customer support, and R&D to identify training needs. Your responsibilities will include developing training materials such as lectures, labs, exams, and demos in alignment with software updates while maintaining high quality standards. As a Training Engineer, you will be involved in creating online and classroom-based training modules, delivering courses in various settings, and producing educational videos to guide customers on tool usage and methodologies. You will also provide support to online training participants and address any queries related to the training content. The ideal candidate for this position is someone who enjoys content creation, learning new tools, and mentoring others. You should be capable of working independently towards set goals and possess a good understanding of analog/mixed-signal design, simulation, and verification processes. Experience in designing and analyzing analog and mixed-signal circuits is essential for this role. Additionally, proficiency in creating test benches for mixed-signal designs using Verilog-A and Verilog-AMS, and familiarity with analog/mixed-signal Cadence design tools like Virtuoso and Spectre are required. Knowledge of SystemVerilog modeling capabilities and exposure to UVM-MS would be advantageous. Candidates applying for this role should hold a Bachelor's or Master's degree in Electrical/Electronics Engineering and have at least 4-6 years of relevant work experience. Strong written and verbal communication skills in English are essential for effectively conveying technical information to diverse audiences. If you are passionate about technology and eager to contribute to meaningful work, we invite you to be part of our collaborative team at Cadence. Join us in our mission to tackle challenges that others cannot solve.,

Description We are seeking an experienced RTL Design Engineer to join our team in India. The ideal candidate will have 6-15 years of experience in designing and verifying RTL for complex digital systems. You will be responsible for creating high-quality RTL designs that meet performance and power specifications. Responsibilities Design and implement RTL code for digital circuits using VHDL or Verilog. Perform functional verification of RTL designs using simulation tools. Collaborate with cross-functional teams to define design specifications and requirements. Optimize designs for performance, area, and power consumption. Debug and troubleshoot RTL designs and resolve any issues during the development process. Participate in design reviews and provide constructive feedback to peers. Skills and Qualifications Proficient in RTL design using VHDL or Verilog. Experience with synthesis tools such as Synopsys Design Compiler or Cadence Genus. Familiarity with digital design principles and methodologies. Knowledge of FPGA and ASIC design flows. Strong understanding of timing analysis and optimization techniques. Experience with simulation tools like ModelSim or QuestaSim. Ability to work collaboratively in a team environment and communicate effectively.

Key Responsibilities 01 years of hands-on experience in implementing designs on FPGA Strong expertise in RTL coding using VHDL/Verilog/System Verilog Understanding of FPGA design flow including constraint definition, synthesis, floor planning, place & route, and timing closure Create block-level design documentation Write testbenches and sequences in SystemVerilog Work with lab equipment for validation and testing Familiarity with standard interface protocols (e.g., SPI, I2C, UART, etc.) Knowledge of modern FPGA architectures Exposure to scripting languages for automation Preferred Experience Hands-on experience with FPGA design tools like Libero Experience with Tcl/Perl/Python scripting Good debugging skills (both hardware and software) Understanding of Clock Domain Crossing (CDC) checks Knowledge of synthesis and static timing analysis Familiarity with FPGA hardware design is an added advantage Benefits Real-world exposure to cutting-edge space technology projects Mentorship from experienced FPGA and space systems engineers Collaborative, growth-oriented team environment Fun, engaging, and fast-paced work culture

You will be joining Insemi Technologies as a Staff or Lead Verification Engineer in Bengaluru. Your primary responsibility will be to own the functional verification of RTL designs for PCIe / UCIe protocols. This will involve building and enhancing UVM testbench components such as scoreboard, driver, and monitor. You will also be debugging complex design/verification issues and collaborating with teams to ensure architecture compliance. Additionally, you will play a key role in improving verification methodology and processes. To excel in this role, you should have at least 5-10 years of verification experience with a strong knowledge of PCIe and/or UCIe protocols. Expertise in SystemVerilog & UVM is essential, along with solid debugging and analytical skills. A degree in B.E/B.Tech or M.E/M.Tech in EE/CE or related fields is required, and any experience in VLSI design services would be a bonus. If you are passionate about PCIe / UCIe protocol verification and possess the necessary skills and experience, we encourage you to send your resume to Jennifer Margaret at jennifer.margaret@insemitech.com. Join us at Insemi Technologies and let's build something exceptional together.,

Qualcomm India Private Limited is seeking a talented individual to join their Wireless IP team for the role of designing and developing cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. In this role, you will be responsible for working on high-performance, low-power digital designs throughout the full VLSI development cycle, from architecture and micro-architecture to RTL implementation and SoC integration. You will have the opportunity to collaborate with global teams and contribute to market-leading wireless solutions. Your key responsibilities will include designing and implementing RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog, developing micro-architecture specifications, integrating complex subsystems into SoC environments, collaborating with various teams such as system architects, verification, SoC, software, DFT, and physical design teams, applying low-power design techniques, analyzing and optimizing for performance, area, and power, ensuring protocol compliance and performance of interconnects, conducting CDC and lint checks, and participating in post-silicon debug and bring-up activities. Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering experience, or - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering experience, or - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. - Minimum qualification of a Bachelors or Masters degree in Electronics, VLSI, Communications, or related field with proven experience in RTL design and SoC development. Preferred Skills & Experience: - 2-5 years of experience in digital front-end ASIC/RTL design. - Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. - Familiarity with wireless protocols such as IEEE 802.11, LTE, or 5G NR is highly desirable. - Solid understanding of bus protocols and bridge logic. - Experience with wireless modem IPs or similar high-performance digital blocks is a plus. - Familiarity with low-power design methodologies and CDC handling. - Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. - Exposure to post-silicon debug and SoC integration challenges. - Strong documentation and communication skills. - Self-motivated with a collaborative mindset and ability to work with minimal supervision. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations to individuals with disabilities during the application/hiring process. For more information about this role, please contact Qualcomm Careers.,

Mandate - Required Skillset RTL Verification Experience: 4–10 years of hands-on experience verifying RTL designs for digital systems or SoCs. Simulation Tools Proficiency: Expertise in using industry-standard verification tools such as ModelSim, Cadence Incisive, and Synopsys VCS. Testbench Development: Proficient at developing and maintaining verification environments and testbenches using SystemVerilog, UVM, Verilog, or VHDL. Functional Verification: Strong background in functional verification, writing test plans, creating test cases, debugging failures, and ensuring design quality. Scripting for Automation: Experience scripting with Python, Perl, or TCL to automate verification workflows and enhance productivity. Coverage Analysis: Familiar with coverage-driven verification methodologies (functional and code coverage). Team Collaboration: Excellent communication and teamwork skills for efficient interaction with design and architecture teams. Problem Solving: Strong analytical skills to identify, debug, and resolve complex design and verification issues. Nice To Have Experience with formal verification tools. Exposure to FPGA prototyping and hardware emulation. Knowledge of industry standard protocols (e.g., AXI, PCIe, USB). Skills: systemverilog,uvm,functional verification,coverage analysis,synopsys vcs,fpga prototyping (nice to have),scripting (python, perl, tcl),verilog,simulation tools (modelsim, cadence incisive, synopsys vcs),testbench development (systemverilog, uvm, verilog, vhdl),python,formal verification tools (nice to have),vhdl,team collaboration,rtl verification,protocol knowledge (axi, pcie, usb - nice to have),modelsim,problem solving,cadence incisive,perl,tcl

Principal Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly-skilled ASIC Digital Verification Engineer with a passion for developing functional verification solutions for RTL based IP Cores. You are experienced in handling complex protocols and thrive in a collaborative international environment. With over 15 years of experience, you possess a deep understanding of verification methodologies and are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM). You are adept at making architectural decisions, implementing test benches, and driving innovation in verification solutions. You are a proactive team player with excellent communication and problem-solving skills, ready to contribute to cutting-edge projects in AI/machine learning, automotive, and server farm applications. What Youll Be Doing: Making architecture decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Utilizing a coverage-driven methodology. Providing technical leadership and guidance to the team. Collaborating with architects, designers, and other verification team members across multiple sites worldwide. The Impact You Will Have: Ensuring the reliability and performance of IP Cores used in critical applications. Driving innovation in verification methodologies and solutions. Contributing to the development of industry-leading technologies in AI, automotive, and server farms. Enhancing productivity and throughput through effective verification strategies. Maintaining high standards of quality and functionality in IP verification. Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement. What Youll Need: Extensive knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience in creating test environments from functional specifications using UVM/VMM/OVM. Proficiency in SystemVerilog (SV), UVM, and object-oriented coding and verification. Ability to provide innovative verification solutions for enhanced productivity and performance. Experience with scripting languages like C/C++, TCL, Perl, Python is an added advantage. Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage Who You Are: You are an independent thinker with a precise approach to work, capable of driving innovation and leading technical projects. Your communication skills are excellent, and you thrive in a team-oriented environment. You are committed to continuous learning and possess a strong problem-solving aptitude. Experience with functional safety standards like ISO26262 and FMEDA is a plus. The Team Youll Be A Part Of: You will be part of the Solutions Group at our Bangalore Design Center, India. This team is dedicated to developing functional verification solutions for IP used in diverse applications, including server farms, AI/machine learning, and automotive sectors. You will work closely with architects, designers, and other verification team members across multiple international sites, contributing to innovative and challenging projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process....Less Show more Show less

About This Opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What You Will Do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Engage in an environment that champions innovation and critical thinking. You'll have the autonomy to explore advanced verification technologies alongside skilled experts. Global Influence: Contribute to projects that transform industries, advance digital economies, and enhance global communication, bridging gaps between people, systems, and information worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you perform at your best without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of designer engineers, providing mentorship and guidance to ensure efficient and reusable design practices and IP. Collect and address, team status and metrics. Own and oversee the breakdown of requirements into actionable tasks for IPs and subsystems, ensuring alignment with project objectives. Review work done by the team, ensuring quality and adherence to design specifications. Take responsibility for deliverables, prioritizing work to ensuring successful completion in time. Continuously enhance and optimize design methodologies and processes, facilitating innovation and efficiency. Collaborate closely with IP System Architects and cross-functional teams to ensure requirements are effectively met. Work closely with the verification lead to support review and refinement of verification plans. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 8+ years of industry experience in ASIC design. Proven track record leading IP development and of successful cross-team and cross-site collaboration. Proficiency in/with: Understanding of ASIC technology, design environments, and methodologies. SystemVerilog RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions. Strong Experience with in low-power design, including specifying power intent using UPF or similar standards. Knowledge of Design for Test methodologies. Additional Requirements: Experience with Cadence and Synopsys front-end and middle-end design suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 766876

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Hyderabad /Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Senior Physical Fri, Mar 28 at 9:39 AM Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad /Bangalore Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

The Verification role requires you to be proficient in Functional and Performance verification, utilizing effective methodologies at different levels such as Module, Subsystem, SoC, and System. It is essential to have the skills to translate requirements into a verifiable plan. You will collaborate with SoC and IP developers locally and globally to implement best practices and enhance productivity continuously. A meticulous approach towards achieving zero defects is crucial. Your responsibilities will include creating verification test benches, verification components, test cases for simulation, formal verification, and emulation. Additionally, you will be responsible for debugging failures and formulating simulation scenarios for various analyses. Your key tasks will involve team leadership, technical guidance, and Verification planning. You will be responsible for developing, fine-tuning, and implementing verification test benches. Furthermore, you will create verification test bench components like drivers, monitors, response checkers, and leverage advanced UVM VIPs. Your role will also entail generating direct and constrained-random stimuli using C and SystemVerilog, examining RTL code, functional coverage, and assertion results. You will be expected to work on functional coverage development and system Verilog assertions. Proficiency in formal verification techniques, robust debugging skills, failure re-creation, and root cause analysis are essential requirements. Strong debugging and logical reasoning skills are crucial for this position. To excel in this role, you must have a strong background in C and UVM/SystemVerilog-based Test environments. Understanding the design/architecture and the ability to debug RTL/Gate netlist are mandatory skills. Coverage-driven Verification expertise is required to fulfill the Functional and Performance requirements of the SoC and manage regression effectively. Knowledge of Microcontroller architecture, ARM Cores, Interconnect (NIC, FlexNoC), Cache Coherency, and Bus Protocols like AHB/AMBA, AXI, ACE is essential. Additional skills that would be advantageous for this role include experience with Memory controllers (Flash, SRAM, DDR3/4/LPDDR), Protocols such as PCIe, MIPI, GPU, Ethernet, and Serial/Quad flash. Familiarity with Formal verification methodologies and Apps, AVIP, PinMuxing Verification, Randomization, and Low Power intent verification using UPF is beneficial. Exposure to pre-silicon validation/emulation tools like Veloce, Zebu, FPGA Prototyping would be considered a plus.,

As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulations will be part of your responsibilities. It is essential to develop and maintain design documentation such as micro-architecture specs and power intent specifications. Supporting integration and implementation teams in handling low power design constraints and challenges will also be a key aspect of your role. To be successful in this position, you should hold a Bachelors or Masters degree in Electronics/Electrical Engineering or a related discipline. With a minimum of 7 years of ASIC front-end design experience, including at least 3 years focused on low power/UPF design, you should be proficient in RTL coding using Verilog/SystemVerilog with strong design fundamentals. A deep understanding of low power architecture techniques like power gating, retention, isolation, and voltage scaling is required. Hands-on experience with UPF-based flows and power-aware tools from Synopsys, Cadence, or Mentor is essential. Experience in running LINT, CDC, and synthesis with power intent, along with excellent debugging and problem-solving skills, are also necessary. Preferred skills include exposure to DFT constraints and the impact of power intent on scan/ATPG, familiarity with scripting languages like Python/Perl/TCL for automation, and experience in collaborating across global design and verification teams. A working knowledge of timing closure, clock domain crossing (CDC), and logic equivalence checks (LEC) would be beneficial in this role. Joining BOLTCHIP will offer you the opportunity to be part of a cutting-edge semiconductor design team focused on innovation and quality. You will collaborate with top-tier professionals in the low-power design domain and benefit from competitive compensation and opportunities for growth. If you meet the requirements and are excited about this opportunity, please apply by sending your resume to jasmine.h@boltchip.com.,

Build your career with Sykatiya Technologies. Sykatiya Technologies values technical ability and attitude within its highly talented team, which is reflected in the contributions made to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. This position is for IP/SOC/ASIC Verification with a required experience level of 3-20 years. The location for this role is in Bangalore & Hyderabad. As a member of the ASIC verification team, you will be responsible for the functional verification of ASIC IPs. The verification methodology utilizes advanced techniques and tools such as coverage-driven constrained random verification and formal verification. Object-oriented architectures and frameworks play a crucial role in the design and implementation of verification environments. The ideal candidate will possess expertise and aptitude in verifying functions like image processing, video compression, and computer vision. Additionally, as a verification engineer, you will have the opportunity to delve into the algorithms supporting the hardware. We are seeking an experienced engineer with exceptional programming skills and a genuine interest in ASIC verification. The verification environments at Sykatiya Technologies are complex, requiring individuals who can comprehend, implement, and maintain intricate software systems effectively. Preferred qualifications for this role include prior experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods. The ideal candidate is expected to be analytical, systematic, and detail-oriented in their approach. Join our team at Sykatiya Technologies and be a part of a dynamic environment where your skills and expertise in ASIC verification will be valued and nurtured.,

As a Verification Engineer at Marvell, you will play a crucial role in leading the verification efforts for blocks, subsystems, and top-level verification. You will be responsible for developing and maintaining UVM-based verification environments, defining and reviewing test plans with architecture and design teams, and verifying designs using directed and constrained random techniques. Your expertise will be utilized to maintain regression, debug failures, and analyze coverage, driving verification to meet coverage targets. You will also contribute to next-generation data processing and hardware accelerator verification, focusing on networking domain verification for future solutions, and ensuring design closure using innovative and automated techniques. To excel in this role, you should possess a Bachelors or Masters degree in Computer Science, Electrical Engineering, or a related field with 8+ years of professional experience. Your strong experience with Verilog, SystemVerilog, and UVM, along with expertise in unit and subsystem verification and modern verification concepts, will be essential. Proficiency in SystemVerilog, C, C++, and scripting (Perl, Tcl, Python preferred) is required, as well as strong debugging skills and verification flow optimization. You will collaborate with design teams on specs, test plans, and verification strategies, develop and maintain UVM-based testbenches for ASIC SoCs, execute verification, maintain regressions, and debug failures. Excellent verbal and written communication skills will also be important in this role. At Marvell, you will be part of a team that is empowering the global data economy. With competitive compensation and great benefits, you will enjoy a workstyle within an environment of shared collaboration, transparency, and inclusivity. Marvell is dedicated to providing its employees with the tools and resources they need to succeed in doing work that matters, and to grow and develop within the company. For more information on what it's like to work at Marvell, visit our Careers page.,

As a Verification Engineer at Google, you will play a crucial role in the development of custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process behind products that are cherished by millions globally. Your expertise will be pivotal in shaping the upcoming generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. Your primary responsibility will involve planning and executing the verification of the next generation configurable Infrastructure Internet Protocols (IPs), interconnects, and memory subsystems. You will be tasked with creating and refining constrained-random verification environments using SystemVerilog, as well as developing cross-language tools and scalable verification methodologies. In this role, you will be expected to identify and implement various coverage measures for stimulus and corner-cases, ensuring comprehensive testing coverage. Collaborating closely with design engineers, you will debug tests to deliver functionally correct blocks and subsystems, while also closing coverage measures to pinpoint verification gaps and showcase progress towards tape-out. To be successful in this position, you should possess a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. Additionally, experience in verifying digital reasoning at the Register-Transfer Level (RTL) using SystemVerilog or C/C++, along with familiarity with verification components and environments in standard verification methodology, is essential. Proficiency in coding languages, software development frameworks, and experience with digital systems using standard Internet Protocols (IP) components/interconnects will be advantageous. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or Computer Science, or equivalent practical experience. A background in architecture with a focus on Hierarchies, Coherency, Memory Consistency Models, and experience with verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes will be beneficial. Additionally, experience with performance verification of Systems on a Chip (SOCs), pre-Silicon analysis, post-Silicon correlation, and Interconnect Protocols would be advantageous. Join our dynamic team at Google, where we combine the best of Google AI, Software, and Hardware to create innovative and helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to improve people's lives through technology.,

As a Silicon Design Engineer 2 at AMD, your role involves collaborating with formal experts and designers to verify formal properties and drive convergence. You will have the opportunity to work on modern, complex processor architecture, digital design, and verification in a team-oriented environment. Your strong analytical and problem-solving skills will be pivotal in understanding design specifications and creating scenarios to verify the design effectively. Communication skills are essential as you coordinate with RTL engineers to implement logic design for improved clock gating and verify different aspects of the design. Your responsibilities will include writing tests, sequences, and testbench components in SystemVerilog and UVM to achieve verification of the design. You will be accountable for verification quality metrics such as pass rates, code coverage, and functional coverage. Prior experience in design concepts and RTL implementation at the project level would be advantageous. Familiarity with formal tools and functional verification tools by VCS, Cadence, or Mentor Graphics is preferred. A solid understanding of computer organization and architecture is also important for this role. To excel in this position, you should possess a Bachelor's or Master's degree in computer engineering or Electrical Engineering. AMD offers a supportive work culture that values innovation, collaboration, and diversity. Join us in advancing next-generation computing experiences and being part of a team that pushes the boundaries of technology.,

The Rivos Power team is seeking a highly motivated engineer to develop and strategically drive state-of-the-art power modeling and optimization across our CPU and SoC blocks.In this role, you will have the opportunity to work in an innovative, collaborative, and high-growth environment. The ideal candidate will possess in-depth experience in the full spectrum of silicon power reduction. This includes a foundation in solid power analysis, performance benchmarking, and design optimization at all levelsfrom microarchitecture and physical implementation to standard power-performance benchmarking. What You&aposll Do Model and analyze power consumption for various workloads on custom silicon, working closely with the CPU Architecture, Performance, and Implementation teams to define overall power requirements. Analyze power and performance trade-offs, drive detailed cost-benefit analyses, and make recommendations for power reduction strategies. Collaborate with the Performance, Design Verification, and RTL teams to create targeted test vectors that model appropriate workloads and functionality scenarios for accurate simulation. Own the end-to-end power simulation process, including analysis, tuning, correlation, and presenting results to the Architecture, Logic Design, and Physical Design teams. Partner with the CAD and Physical Design teams to enhance power estimation methodologies, simulation flows, and regression analysis. What You&aposll Bring A Bachelor&aposs or Master&aposs degree in EE/EECS with 4-7 years of relevant industry experience. 4 to 7 years of direct experience in power-aware design, including analysis, benchmarking, modeling, and simulation. Strong working knowledge of CPU architectures and workload modeling for power analysis. Familiarity with the RISC-V architecture is a significant plus. Proficiency with Verilog and SystemVerilog RTL coding. Experience with the complete silicon design flow and evaluating power, performance, and area (PPA) trade-offs at the architectural, logic, and circuit levels. Hands-on experience with state-of-the-art EDA tools for gate-level and transistor-level power modeling and simulation. Strong scripting skills in Python, TCL, or other relevant languages. A proven ability to solve problems dynamically, innovate, drive decisions, and lead team efforts to deliver results under aggressive schedules. Show more Show less

Job Titles: Senior Staff ASIC Verification Engineer- Pune Location We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and passionate ASIC Digital Verification engineer, ready to take on technical leadership in a dynamic, high-impact environment. With a proven track record of developing and validating complex UVM verification environments, you thrive in collaborative settings and enjoy mentoring others. You bring a deep understanding of digital verification flows, simulation, and coverage analysis, and you excel at identifying and solving challenging design problems. Your experience spans 8-15+ years in ASIC verification, where you&aposve consistently demonstrated your ability to architect, plan, and execute verification strategies. Youre comfortable multitasking between multiple projects and have a genuine desire to stay at the forefront of emerging technologies. You communicate effectively in both written and spoken English, and your organizational skills help ensure that projects are delivered on time and to the highest quality standards. Youre motivated by the opportunity to make a significant impact, not just through your own work, but by elevating the entire team around you. Your proactive approach to learning, problem-solving, and process improvement defines your professional ethos. What Youll Be Doing: Identify verification environment requirements from specifications, design functionalities, and interfaces. Generate comprehensive verification test plans and maintain detailed documentation for verification environments and their usage. Define, develop, and verify advanced UVM (Universal Verification Methodology) environments for complex ASIC designs. Evaluate and exercise all aspects of the verification flow, including Verilog/SystemVerilog development, functional simulation, constraint development, behavioral modeling, and coverage metrics analysis (functional and code coverage). Collaborate closely with architects, designers, and the VIP team to ensure seamless integration and accomplishment of project goals. Identify design problems, propose corrective actions, and resolve inconsistencies in documented functionalities. Mentor and guide junior engineers, supporting them in debugging and solving complex verification problems. Support customer issues through issue reproduction and in-depth analysis, ensuring customer satisfaction. Drive continuous improvement of verification methodologies and execution efficiency within the team. Adhere to best practices, quality standards, and maintain a high level of test and verification rigor. The Impact You Will Have: Accelerate the delivery of robust, high-quality ASIC products by ensuring thorough and systematic verification. Enhance the teams technical capabilities by sharing expertise and mentoring junior engineers. Directly contribute to Synopsys reputation for excellence in silicon design and verification solutions. Drive innovation in verification methodologies, raising the bar for future projects and industry standards. Improve customer satisfaction by providing expert support and resolving technical challenges efficiently. Facilitate cross-functional collaboration, fostering a culture of knowledge sharing and continuous learning. What Youll Need: 8-15+ years of hands-on experience in ASIC digital verification, preferably in a lead or staff engineering capacity. Proficiency in Verilog, VHDL, and/or SystemVerilog languages, with a strong grasp of modern verification methodologies such as UVM. Experience in developing and debugging verification environments, including test planning, simulation, and coverage analysis. Familiarity with industry-standard scripting languages (BASH, TCSH, PERL, PYTHON, TCL) for automation and workflow optimization. Excellent written and spoken English communication skills, with the ability to document and present technical concepts clearly. Strong organizational skills, with experience managing multiple priorities and delivering high-quality results under tight deadlines. Who You Are: Innovative and proactive, with a passion for continuous learning and embracing new technologies. Collaborative team player who thrives in a diverse, multicultural environment. Analytical thinker with exceptional problem-solving and troubleshooting abilities. Effective mentor and leader, capable of guiding and inspiring junior engineers. Detail-oriented and process-driven, committed to delivering excellence in every project. Resilient and adaptable, able to multitask and manage shifting priorities in a fast-paced setting. The Team Youll Be A Part Of: You will join a world-class team of verification engineers dedicated to delivering high-performance, reliable ASIC solutions. Our team values technical excellence, innovation, and collaboration. We work closely with architects, designers, and validation teams to ensure robust product delivery. As a senior member of the team, you will have the opportunity to influence verification strategies, lead technical initiatives, and mentor the next generation of engineering talent at Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"