Senior Design Verification Engineer

Senior Design Verification Engineer

Experience : 5-10 years

Location : Hyderabad

Functional Verification Engineer

Role Summary:

Functional Verification Engineer

Key Responsibilities:

• Develop and maintain

  block-level testbenches

  using SystemVerilog/UVM.
• Create and execute

  verification plans (Vplan)

  , run regressions, and achieve coverage closure.
• Work on

  testbenches with real number modeling

  .
• Perform

  netlist and gate-level simulations

  .

Qualifications & Experience:

• Education:

  Bachelor’s degree or higher in Electronics or related field.

• Experience:

  5–10 years in functional verification.

• Skills:

• Hands-on coding in

  SystemVerilog/UVM

  .
• Experience with block/IP-level verification; subsystem or SoC-level experience is a plus.

• Soft Skills:

  Strong communication, ability to work independently and meet schedules.

Interested,please share your updated resume to janagaradha.n@acldigital.com