660 Systemverilog Jobs

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Category Engineering Hire Type Employee Job ID 10795 Remote Eligible No Date Posted 20/04/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 8-12 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 6-10 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective Locally should be to be go-to person on all technical aspects of VIP

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP. Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with Perforce or similar revision control environment. Experience with Python/TCL or any scripting knowledge is an added advantage. Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification. Be single point of contact with hands-on experience on all verification tasks - Testbench Creation - Testplan creation - Coverage closure - SVA - Release Perform peer review of testbench code for continuous quality. Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. Lead team of engineers to perform various verification activities on IPs/Subsystems. Anticipate problems and risks and work towards a resolution and risk mitigation plan. Assist and mentor the team in day-to-day activities and grow the capabilities of verification team for future assignments. Review various results and reports to provide continuous feedback to the team and improve quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. The candidate must have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.

Here's the revised description with bullets and bolded subheadings: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 8-15 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You'll Be Doing: Designing, developing, and troubleshooting core algorithms for word-level synthesis. Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. Engaging in pure technical roles focused on software development and architecture. Implementing multi-threaded and distributed code solutions. Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. Enhancing the performance and quality of synthesis tools used globally. Solving complex logic interference problems to improve design accuracy. Contributing to the development of high-performance silicon chips and software content. Collaborating with cross-functional teams to achieve project milestones. Pioneering new software architectures that set industry standards. What You'll Need: Strong hands-on experience in C/C++ based software development. Deep understanding of design patterns, data structures, algorithms, and programming concepts. Familiarity with multi-threaded and distributed code development. Knowledge of ASIC design flow and EDA tools and methodologies. Proficiency in Verilog, SystemVerilog, and VHDL HDL.

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA What Youll Be Doing: Making architectural decisions on test bench design Writing verification plans and specifications Implementing test bench infrastructure and writing test cases Implementing a coverage-driven methodology Leading technical aspects of verification projects Collaborating with international teams of architects, designers, and verification engineers The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications Driving innovation in verification methodologies and tools Ensuring high-quality deliverables through rigorous verification processes Improving productivity, performance, and throughput of verification solutions Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms Mentoring and guiding junior engineers in the verification domain What Youll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure Proficiency in SystemVerilog and UVM, object-oriented coding, and verification Experience with scripting languages like C/C++, TCL, Perl, Python Experience with functional safety standards such as ISO26262 and FMEDA (preferred) Who You Are: Independent and precise in your work Innovative and proactive in problem-solving Excellent communicator and team player Detail-oriented with a strong analytical mindset Eager to learn and grow within a technical role The Team Youll Be A Part Of: You will join the Solutions Group at our Bangalore Design Center, India This team is dedicated to developing functional verification solutions for IP cores used in various end-customer applications You will work closely with architects, designers, and verification engineers across multiple international sites, fostering a collaborative and innovative environment

You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume production Experience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and/or design-for-test (DFT) Experience with Computer Architecture, Computer Arithmetic, C/C++ programming languages is desiredExposure to DX912 level graphics HW development is big plus Good communication skill and desire to work as a team player Required: Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field.Preferred: Master's degree in Computer Science, Electrical Engineering, Information Systems, or related field. ASIC, hardware, design, GPU, OpenGL, DirectX, RTL, Verilog, System Verilog Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Role: Hardware Platform Engineer

Ownership of a piece of the test bench Planning & execution of feature additions and mode re-enablement on particular variants Bug fixes Debug of regression signatures Developing/Deploying new tools for performance validation Performance monitor and profiler development and deployment Workload specific simulations on the emulator Following skillset is required: Strong Python, C++ skills Reading Specs and developing test plans Monitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening 6 months - 1 Year of industry experiences in the following areas: - Basic of digital design concepts, fifo etc Basic understanding of DDR is a plus Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering Candidate must possess right analytical skills, debug oriented mindset and must be open to discuss , deep dive, collate and present the design and environment understanding . Minimum Qualifications: Associates degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field.

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

To apply to a Varex Imaging position, please create an account and sign-in. CURRENT VAREX IMAGING EMPLOYEES: Please apply by logging into your internal Workday Account. Summary Job Description Summary Analyzes, designs, programs, debugs and modifies FPGA code designs. Troubleshoots code for firmware (IC embedded code) applications. Work often involves analog and digital hardware and software operating systems. Position requires knowledge and exposure to hardware design. Typically, programs in - Hardware Description Languages (e.g., SystemVerilog or VHDL) or high-level languages (e.g., Python) Job Description Varex Imaging is seeking a FPGA / Embedded Firmware Engineer in the fast-growing X-Ray Imaging Components division. This individual will work in our India facility. This developer will bring value to our team by developing firmware systems and libraries needed to process and manage flat panel x-ray detectors data used in medical and industrial imaging systems. We are looking for candidates that will thrive in a fast paced, self-directed environment. This is an opportunity to work both individually and with our team of highly skilled FPGA engineers. This position involves writing HDL code, developing/implementing efficient algorithms that interact with x-ray hardware components and developing low-level component interfaces both in FPGA and embedded software Your Role Experience with Verilog, SystemVerilog and/or VHDL Experience with the basics of FPGA development Familiarity with a simulation tool – Modelsim or equivalent Experience with a scripting language such as Python Some experience with debugging electrical hardware using Chipscope/Signaltap or oscilloscope/logic analyzer Your Profile... B.S. in Electrical Engineering, Physics, Computer Science or related field and 5+ years of relevant experience, or M.S. or Ph.D. with 2+ years of relevant experience Experience with Windows & Linux Familiar with Object-oriented Design and Analysis (OOA and OOD) a plus Development of specifications & requirements Design, build, and unit test firmware in a collaborative environment Knowledge/use of automated test benching a plus Familiarity with the use of FPGA intellectual property beneficial Excellent oral and written communication skills Must be able to work with minimal supervision. Proficient in utilizing business tools such as: E-mail, Microsoft Word, Excel, and PowerPoint. What we offer… A unique opportunity to become part of growing organization in India being part of a global market leader in Xray imaging components. Excellent development potential. An international work environment with global teams collaborating on various projects across several countries. Competitive compensation package including participation in Varex incentive plans. Corporate Health Benefits. Additional benefits will be added as we grow. Time Type: Full time Job Type: Regular Work Shift: N/A Pay Rate Type: Salary All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.

Over 3 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus.

Bangalore,Karnataka,India Job ID 768642 About Us: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What we offer: Leadership Opportunity: Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 12+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification teams of 8+ engineers for minimum 2 years. Experience in test plan development in cross-team and international cross-site environment Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models AMBA-based designs such as AXI and CHI. SystemVerilog Assertions. Strong experience in low-power design verification. Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Additional Requirements Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: Proven hands-on experience verifying some of the industry-standard protocols ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Developing Reference Models in Matlab/Simulink or System C Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

Design Verification Engineer – NoC / VLSI (Product-Based Only) Location: Bangalore, Karnataka Job Type: Full-Time Salary: ₹15 – 30 LPA (Depending on Experience) Experience Required: 5 – 12 Years (Only from Product-Based Companies) Job Overview We are seeking an experienced Design Verification Engineer with strong expertise in NoC (Network-on-Chip) and VLSI verification . The ideal candidate will have a proven track record in product-based semiconductor companies , with deep knowledge of advanced verification methodologies, coverage-driven strategies, and RTL debug. This role offers the opportunity to work on cutting-edge semiconductor solutions with a focus on innovation and high performance. Key Responsibilities Develop and execute comprehensive verification strategies for NoC and related IPs. Build and maintain UVM/SystemVerilog testbenches , including constrained-random tests and functional coverage. Drive coverage closure using functional, assertion, and code coverage metrics. Debug and resolve complex RTL design and simulation issues . Collaborate with design, architecture, and EDA tool teams to define verification requirements and strategies. Automate regression suites, test plans, and reporting using scripting languages (Python, Perl, TCL). Ensure quality sign-off criteria are met before tape-out. Required Skills & Experience 5 – 12 years of experience in Design Verification , exclusively in product-based semiconductor companies . Strong expertise in SystemVerilog , UVM , and modern verification methodologies. Proven experience in NoC (Network-on-Chip) verification. Hands-on experience with coverage-driven verification and assertion-based verification . Proficient with industry-standard simulation tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Strong scripting skills in Python, Perl, or TCL . Excellent debugging skills for complex RTL issues. Familiarity with UNIX/Linux development environments. Strong communication, analytical, and problem-solving skills. Preferred Qualifications Experience with formal verification and low-power verification techniques. Exposure to SOC-level verification . Experience in cross-site collaboration and working with global teams. Job Types: Full-time, Permanent Pay: ₹1,500,000.00 - ₹3,000,000.00 per year Benefits: Health insurance Provident Fund Work Location: In person

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts – Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electronics/Electrical Engineering #LI-SR5 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AI Centre Ethernet Switching Architect India-remote. person could be based anywhere in India - Remote work will be considered for exceptional profiles Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore AI Centre Ethernet Switching Architect Position Overview We are seeking a top-notch specialist Architect with over 15 years of experience to join our team in designing and developing Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet/TCP/IP protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, UALink, Ultra Ethernet with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Define and develop the architecture of AI Datacentre Switch Fabric from ground up Performance Modelling and optimization of latency, throughput and power efficiency of switch fabric Decompose the architecture into sub blocks for implementation by design team Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control, packet spraying Apply knowledge of InfiniBand/Ultra Ethernet, NVLink/UALink, or similar protocols for feature implementation. Understanding/experience of IOS/Junos or equivalent software platform Use P4 or related languages for programmable packet processing. Working with design, software, verification team for complete product solutions Documentation of architecture and stay updated on AI networking trends. Required Qualifications Education: MS/PhD in Electrical/Electronic Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Soft Skills: Strong problem-solving, communication, and teamwork skills. Position Overview Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to achieve SoC functional and performance goals. Strong proficiency in DSP architectures, AMBA protocols, and RTL coding is required, along with proven ability to deliver high-quality designs. Preferred skills include Matlab/NumPy/C/C++, high-speed SerDes, FPGA-based validation, and post-silicon bring-up.

Role Description: A highly skilled VLSI Frontend Design Engineer with hands-on experience in architecting and developing complex SoCs from scratch. Exp: 8+ years Location: Trivandrum. Experience: 8–10 years in VLSI Frontend & RTL Design, with at least one complete end-to-end SoC development ownership. Strong RTL Design Expertise: Verilog, SystemVerilog, VHDL. Micro-architecture Design: Experience defining and implementing high-performance compute or control-intensive SoC subsystems. Interface & Protocol Knowledge: AMBA (AXI/AHB/APB), PCIe, DDR, USB, MIPI, I2C/SPI, Ethernet, etc. EDA Tools: Synopsys/Cadence/Siemens front-end tools (Design Compiler, Spyglass, VCS, Incisive, etc.). Power-aware Design Techniques: Clock gating, multi-Vt, UPF/CPF based design. Good understanding of DFT, CDC, Linting, Synthesis constraints , timing closure. Exposure to RISC-V/ARM architecture , cache design, coherency protocols, and IO subsystems. Strong documentation skills, design reviews, and collaboration in cross-functional teams. Experience with AI/ML accelerators , Automotive/ADAS SoCs, or high-speed SerDes. (Good to have) Knowledge of High-Level Synthesis (HLS) flows and SystemC modeling. Familiarity with firmware/embedded software and driver bring-up. Educational Qualification: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, VLSI, or equivalent from a reputed institute.

1. Strong coding with Verilog and SystemVerilog 2. Good knowledge of AHB,AXI, AMBA protocol, exp in Ethernet 3. Many experiences with sequence creation, functional cover groups and assertion coding. 4. Strong C/C++ software development experiences 5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby. Show more Show less

About the Role: We are seeking a highly experienced Verification Engineer to join our dynamic team, driving innovation in advanced verification methodologies for complex semiconductor designs. You will play a key role in architecting, developing, and deploying verification methodologies for industry-leading IPs and sub-systems. Key Responsibilities: Lead the deployment of verification tools, platforms, and strategies for complex IPs Drive simulation-based and hardware-assisted verification efforts, including debugging and root cause analysis Apply expertise in a broad range of verification technologies, including simulation, static, and formal verification Develop and enhance verification methodologies, including verification cockpits and CAD flows Collaborate cross-functionally with IP design and DV teams as well as tools teams to ensure product quality Mentor and guide junior engineers, fostering a culture of technical excellence Qualifications: 10+ years of experience in verification engineering for complex hardware systems Deep expertise in simulation and debug, with a proven track record of silicon success Hands-on experience with Static/ Formal verification tools and methodologies Experience developing and deploying verification methodologies, including verification cockpits and CAD flows Exposure to hardware-assisted verification environments (FPGA prototyping, emulation) is a strong plus Strong analytical, problem-solving, and communication skills Bachelors or Masters in Electrical Engineering, Computer Engineering, or related field Familiarity with industry-standard verification languages (SystemVerilog, UVM, SVA) Experience with scripting and automation (Python, Perl, TCL) Track record of technical leadership and cross-functional collaboration Why Synopsys: Join a team that powers innovation and values agility, courage, excellence, and trust. We offer opportunities to work on cutting-edge technology and make a real impact. Show more Show less

Job Overview Experience: 3 – 15 years Responsibilities Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks—defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills And Experience Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Job Title: Design Verification Engineer Experience: 10+ Company: Avecas Job Overview: We are seeking motivated Design Verification Engineers to join our VLSI team. The role involves verifying complex digital designs at block and SoC level using advanced methodologies to ensure functional correctness, quality, and performance. Key Responsibilities: Develop and execute test plans, testbenches, and verification environments . Work on SystemVerilog/UVM-based verification . Create and run directed, constrained-random, and regression tests . Debug and resolve design/verification issues using EDA tools. Collaborate with RTL design, architecture, and physical design teams. Document verification results and maintain coverage metrics. Required Skills: Strong knowledge of Digital Design and Verilog/SystemVerilog . Understanding of functional verification methodologies (UVM/OVM). Hands-on experience with EDA tools (simulation, debugging, coverage analysis). Familiarity with scripting languages (Python, Perl, TCL, Shell) is a plus. Good problem-solving, debugging, and communication skills. Nice to Have (for experienced candidates): Exposure to SoC-level verification . Knowledge of low power verification, CDC, or formal verification . Experience in industry-standard simulators and verification IPs . Why Join Us? ✅ Opportunity to work on cutting-edge SoC/ASIC projects . ✅ Collaborative and learning-driven environment. ✅ Growth opportunities in the VLSI design & verification domain.

Job Requirements Job Title: Senior Design Verification Engineer We are currently seeking a Senior Design Verification Engineer to join our team on a temporary basis. As a key member of our engineering team, you will be responsible for verifying and validating complex digital designs to ensure they meet the highest quality standards. Key Responsibilities: Develop and execute verification plans for digital designs Write test benches and test cases to verify functionality Collaborate with design engineers to identify and resolve issues Analyze and debug failures to improve design quality Stay current on industry trends and best practices in design verification Qualifications: Bachelor's degree in Electrical Engineering or related field Proven experience in design verification of digital designs Proficiency in Verilog/SystemVerilog and UVM methodology Strong problem-solving skills and attention to detail Excellent communication and teamwork abilities If you are a talented Design Verification Engineer looking to make an impact in a dynamic and innovative environment, we would love to hear from you. Apply now to join our team!

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements Preferred Experience Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts - Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. Academic Credentials Bachelors or Masters degree in computer engineering/Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.