1434 Systemverilog Jobs

Responsibilities: Define, develop, verify and optimize complex digital circuits for low-power mixed-signal circuits. Design digital hardware functions and sub/full systems in RTL code using SystemVerilog, Verilog or VHDL. Collaborate with system design to create digital specification definition. Implement design for testability (scan chain, BIST, boundary scan) and diagnosis features to support hardware testing. Generate technical documentation and drive design reviews. (40%) Define constraints, perform logic synthesis, implement or supervise physical design for timing closure, perform DFT insertion and create test vectors, perform static timing closure. (10%) Support development of comprehe...

Responsibilities: Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%) Design and implement complex testbenches using SystemVerilog and UVM methodology. Perform block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) ver...

Responsibilities: Define, develop, verify and optimize complex digital circuits for low-power mixed-signal circuits. Design digital hardware functions and sub systems in RTL code using SystemVerilog, Verilog or VHDL. Collaborate with system design to create digital specification definition. Implement design for testability (scan chain, BIST, boundary scan) and diagnosis features to support hardware testing. Generate technical documentation and participate in design reviews. (40%) Support constraints definition, logic synthesis, and physical design for timing closure, DFT insertion and test vectors creation, static timing closure. (15%) Support development of comprehensive verification plans ...

Job ID 486088 Posted since 21-Nov-2025 Organization Digital Industries Field of work Research & Development Company SIEMENS EDA (INDIA) PRIVATE LIMITED Experience level Experienced Professional Job type Full-time Work mode Office/Site only Employment type Permanent Location(s) Noida - Uttar Pradesh - India Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design....

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

Job ID 486088 Posted since 21-Nov-2025 Organization Digital Industries Field of work Research & Development Company SIEMENS EDA (INDIA) PRIVATE LIMITED Experience level Experienced Professional Job type Full-time Work mode Office/Site only Employment type Permanent Location(s) Noida - Uttar Pradesh - India Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design....

Role Overview: As a PSS Verification Lead at Vayavya Labs, you will play a crucial role in understanding customer requirements related to system-level verification scenarios. Your responsibilities will include developing test scenarios in PSS language and in C or SystemVerilog/UVM as necessary, executing these scenarios in pre-silicon and post-silicon environments, and debugging them efficiently. You will be contributing to the advancement of Portable Stimulus (PSS) technology and working on developing PSS-based scenarios for various SoC sub-systems, such as PCIe, UCIe, CXL, GPU, MIPI CSI/DSI, and Ethernet. Key Responsibilities: - Understand customer requirements for system-level verificatio...

Role Overview: You will be joining Eviden as an ASIC Verification Lead based in Bangalore (Whitefield). With 8+ years of experience and a Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) in Electronics and Communication Engineering, you will play a crucial role in integrating the ASIC functional verification team. Your main focus will be on verifying ASICs such as network controllers, routers, and cache coherence controllers for high-end and high-performance servers. By utilizing Constraint-Random and Coverage Driven methodologies under the UVM verification framework, you will ensure thorough verification of complex ASIC designs. Key Responsibilities: - Acquire in-depth knowled...

4 to 10 years experience in SoC/Subsystem Design Verification SystemVerilog and UVM Testbench creation experience is a must Own and drive Defining/Implementation of test plans Debugging complex issues Completion of coverage including gate-level simulations Experience in writing SVA (SystemVerilog Assertions) is a must Protocol Expertise (Deep knowledge and hands-on expertise) on one or more of the following PCIe, UCIe, CXL, or NVMe AXI, ACE or CHI Ethernet DDR, LPDDR or HBM Should have worked on verification of at least three full-chip/subsystem DV projects EDA tools Synopsys VCS/ Cadence Xcelium and Verdi debugger Experience of Power Aware Simulations using UPF is desirable (not a must) Exp...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...

5+Yrs of Experience in Verification Own UVM-based constrained-random verification for complex SoC/IP subsystems. Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC/CC/SC). Must have SystemVerilog/UVM, assertions (SVA), functional coverage, and regressions. Experience with bus protocols (AXI/AHB/APB/PCIe), cache/Coherency, and interrupts. Debug with waveforms, CDC/RDC awareness, lint, and formal/property checks. Tools: VCS/Questa/Xcelium, Verdi/DVE, Jenkins/CI, code reviews. Strong scripting (Python/Perl/TCL), Make/CMake, version control (Git). Work with architects/design/DFT/PD for spec clarification and sign-off

5+Yrs of Experience in Verification Own UVM-based constrained-random verification for complex SoC/IP subsystems. Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC/CC/SC). Must have SystemVerilog/UVM, assertions (SVA), functional coverage, and regressions. Experience with bus protocols (AXI/AHB/APB/PCIe), cache/Coherency, and interrupts. Debug with waveforms, CDC/RDC awareness, lint, and formal/property checks. Tools: VCS/Questa/Xcelium, Verdi/DVE, Jenkins/CI, code reviews. Strong scripting (Python/Perl/TCL), Make/CMake, version control (Git). Work with architects/design/DFT/PD for spec clarification and sign-off

5+Yrs of Experience in Verification Own UVM-based constrained-random verification for complex SoC/IP subsystems. Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC/CC/SC). Must have SystemVerilog/UVM, assertions (SVA), functional coverage, and regressions. Experience with bus protocols (AXI/AHB/APB/PCIe), cache/Coherency, and interrupts. Debug with waveforms, CDC/RDC awareness, lint, and formal/property checks. Tools: VCS/Questa/Xcelium, Verdi/DVE, Jenkins/CI, code reviews. Strong scripting (Python/Perl/TCL), Make/CMake, version control (Git). Work with architects/design/DFT/PD for spec clarification and sign-off

In this role, you will be part of the ASIC verification team responsible for functional verification of ASIC IPs. ASIC verification methodology employs state-of-the-art techniques and tools, including coverage-driven constrained random verification and formal verification. Object-oriented architectures and frameworks are a fundamental part of how we design and implement our verification environments. Expertise and aptitude towards verifying functions such as image processing, video compression, and computer vision. As a verification engineer, you will also have the opportunity to learn about the algorithms behind the hardware. **Key Responsibilities:** - Responsible for functional verificati...

Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. Responsibilities: Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. Own design bring-up, block/subsystem integration, and close on timing, power, and area with synthesis and PnR teams. Drive design reviews, close bugs, and support silicon validation and post-silicon debug. Collaborate with DV to define test plans, assertions, and coverage goals; support emulation/FPGA only as a secondary validation aid (not counted toward the 10 years). Must-have qualifications: 10+ years o...

As a Senior/Principal ASIC RTL Design Engineer at our company based in Bangalore, Karnataka, you will have the opportunity to take ownership of the end-to-end RTL design process for complex SoC or large subsystem blocks. Your responsibilities will include defining micro-architecture from specs, writing high-quality synthesizable SystemVerilog/Verilog RTL, and ensuring successful tapeout and silicon bring-up. Responsibilities: - Define micro-architecture and write synthesizable RTL for SoC-level or large subsystems. - Own design bring-up, integration, and ensure timing, power, and area targets are met. - Lead design reviews, bug resolution, and support silicon validation and post-silicon debu...

As a Design Verification Engineer at our company, you will play a crucial role in ensuring the functionality and performance of our high-speed interfaces such as DDR, PCIe, UCIe, and NVMe. Your responsibilities will include: - Conducting design verification for high-speed interfaces using SystemVerilog and UVM methodologies - Developing efficient and reusable verification components like scoreboards, monitors, and sequencers - Collaborating with the design team to debug and resolve issues using tools such as Waveform Viewers and Logic Analyzers - Staying updated with industry standards and protocol specifications for interfaces like DDR, PCIe, UCIe, and NVMe - Utilizing simulation tools like...

As a FPGA Development Team Lead at Optiver, you will play a crucial role in shaping the future of the company's execution platforms in Mumbai, India. You will be part of the founding team responsible for achieving best-in-market trade execution on Indian exchanges such as NSE, BSE, and MCX. Collaboration with established FPGA & low latency development teams in Sydney and Shanghai will provide you exposure to global challenges in trade execution. Your responsibilities will include: - Building and leading a high-performance mixed FPGA development & low latency software development team - Defining the architecture of the ultra low latency trading stack in collaboration with senior developers - ...

As a member of the team at Cadence, you will be responsible for designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your role will involve creating RTL for DFT IP, including POST and IST. Additionally, you will be developing synthesis automation for DFT IP, which includes synthesis and timing constraints, RTL insertion, and verification. You will also have the opportunity to own, maintain, extend, and enhance existing DFT IP like LBIST. Qualifications required for this role: - Proficiency in Verilog/SystemVerilog and/or VHDL - Experience in designing and implementing DFT IP - Knowledge of synthesis automation for DFT IP - Familiarity with POST, IST, LBIST, synthesis, a...

As an FPGA Engineer specializing in Image Processing for Avionics, your role will involve designing, developing, verifying, and optimizing FPGA-based image processing systems used in advanced airborne vision and sensor platforms. Your responsibilities will include: - Designing, implementing, and verifying FPGA-based architectures for real-time image and video processing in avionics applications. - Developing RTL code (VHDL/Verilog/SystemVerilog) for high-speed image pipelines, compression, and filtering algorithms. - Integrating FPGA modules with embedded processors (e.g., ARM, MicroBlaze, Nios) and external interfaces such as ARINC818, ARINC429, PCIe, HDMI, DVI, LVDS, DDR4/3/2 & Ethernet, U...

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the aw...

As a Senior Design Verification Engineer, you will be responsible for building UVM-based testbenches from scratch and contributing to multiple successful tapeouts. Your deep expertise in functional verification using SystemVerilog and UVM will be essential, along with owning verification deliverables end-to-end. Key Responsibilities: - Develop UVM-based testbenches from scratch - Contribute to multiple successful tapeouts - Utilize strong hands-on experience with SystemVerilog and UVM methodology - Apply solid knowledge of SoC/ASIC architecture and verification lifecycle - Write testbenches, stimulus, checkers, monitors, and scoreboards - Demonstrate strong debugging skills using simulation ...

Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT readiness. Collaborate with verification teams for test planning, debugging, and coverage closure. Integrate IPs into top-level SoC and resolve timing and functionality issues. Support emulation, FPGA prototyping, and silicon bring-up activities with cross-functional teams.

Hi All, Greetings from Eximietas Design ....! We are Hiring RTL Micro Architect Engineers/Leads ...! Job Title: RTL Micro Architect. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Eximietas Design is seeking an experienced and highly skilled RTL Micro Architect to join our growing team. As a key contributor, you will play a critical role in defining and implementing the microarchitecture of cutting-edge semiconductor designs. You will work on complex RTL design challenges, collaborate with cross-functional teams, and contribute to the delivery of high-performance, power-efficient, an...

Description Job Title : AMS Verification Engineer Location : : 812 Years Education : Bachelors or Masters in Electronics / Electrical Engineering / Microelectronics / Computer Science About The Role We are looking for a highly skilled and experienced AMS Verification Engineer to join our team in Bangalore. The ideal candidate will have hands-on expertise in SoC/IP-level verification using AMS methodologies, along with a strong understanding of both analog and digital design domains. This role requires deep technical knowledge, problem-solving ability, and collaboration with cross-functional teams across global sites. Key Responsibilities Lead and execute AMS verification for complex IPs and ...