675 Systemverilog Jobs - Page 2

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

To apply to a Varex Imaging position, please create an account and sign-in. CURRENT VAREX IMAGING EMPLOYEES: Please apply by logging into your internal Workday Account. Summary Job Description Summary Analyzes, designs, programs, debugs and modifies FPGA code designs. Troubleshoots code for firmware (IC embedded code) applications. Work often involves analog and digital hardware and software operating systems. Position requires knowledge and exposure to hardware design. Typically, programs in - Hardware Description Languages (e.g., SystemVerilog or VHDL) or high-level languages (e.g., Python) Job Description Varex Imaging is seeking a FPGA / Embedded Firmware Engineer in the fast-growing X-Ray Imaging Components division. This individual will work in our India facility. This developer will bring value to our team by developing firmware systems and libraries needed to process and manage flat panel x-ray detectors data used in medical and industrial imaging systems. We are looking for candidates that will thrive in a fast paced, self-directed environment. This is an opportunity to work both individually and with our team of highly skilled FPGA engineers. This position involves writing HDL code, developing/implementing efficient algorithms that interact with x-ray hardware components and developing low-level component interfaces both in FPGA and embedded software Your Role Experience with Verilog, SystemVerilog and/or VHDL Experience with the basics of FPGA development Familiarity with a simulation tool – Modelsim or equivalent Experience with a scripting language such as Python Some experience with debugging electrical hardware using Chipscope/Signaltap or oscilloscope/logic analyzer Your Profile... B.S. in Electrical Engineering, Physics, Computer Science or related field and 5+ years of relevant experience, or M.S. or Ph.D. with 2+ years of relevant experience Experience with Windows & Linux Familiar with Object-oriented Design and Analysis (OOA and OOD) a plus Development of specifications & requirements Design, build, and unit test firmware in a collaborative environment Knowledge/use of automated test benching a plus Familiarity with the use of FPGA intellectual property beneficial Excellent oral and written communication skills Must be able to work with minimal supervision. Proficient in utilizing business tools such as: E-mail, Microsoft Word, Excel, and PowerPoint. What we offer… A unique opportunity to become part of growing organization in India being part of a global market leader in Xray imaging components. Excellent development potential. An international work environment with global teams collaborating on various projects across several countries. Competitive compensation package including participation in Varex incentive plans. Corporate Health Benefits. Additional benefits will be added as we grow. Time Type: Full time Job Type: Regular Work Shift: N/A Pay Rate Type: Salary All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.

Over 3 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus.

Bangalore,Karnataka,India Job ID 768642 About Us: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What we offer: Leadership Opportunity: Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 12+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification teams of 8+ engineers for minimum 2 years. Experience in test plan development in cross-team and international cross-site environment Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models AMBA-based designs such as AXI and CHI. SystemVerilog Assertions. Strong experience in low-power design verification. Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Additional Requirements Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: Proven hands-on experience verifying some of the industry-standard protocols ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Developing Reference Models in Matlab/Simulink or System C Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

Design Verification Engineer – NoC / VLSI (Product-Based Only) Location: Bangalore, Karnataka Job Type: Full-Time Salary: ₹15 – 30 LPA (Depending on Experience) Experience Required: 5 – 12 Years (Only from Product-Based Companies) Job Overview We are seeking an experienced Design Verification Engineer with strong expertise in NoC (Network-on-Chip) and VLSI verification . The ideal candidate will have a proven track record in product-based semiconductor companies , with deep knowledge of advanced verification methodologies, coverage-driven strategies, and RTL debug. This role offers the opportunity to work on cutting-edge semiconductor solutions with a focus on innovation and high performance. Key Responsibilities Develop and execute comprehensive verification strategies for NoC and related IPs. Build and maintain UVM/SystemVerilog testbenches , including constrained-random tests and functional coverage. Drive coverage closure using functional, assertion, and code coverage metrics. Debug and resolve complex RTL design and simulation issues . Collaborate with design, architecture, and EDA tool teams to define verification requirements and strategies. Automate regression suites, test plans, and reporting using scripting languages (Python, Perl, TCL). Ensure quality sign-off criteria are met before tape-out. Required Skills & Experience 5 – 12 years of experience in Design Verification , exclusively in product-based semiconductor companies . Strong expertise in SystemVerilog , UVM , and modern verification methodologies. Proven experience in NoC (Network-on-Chip) verification. Hands-on experience with coverage-driven verification and assertion-based verification . Proficient with industry-standard simulation tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Strong scripting skills in Python, Perl, or TCL . Excellent debugging skills for complex RTL issues. Familiarity with UNIX/Linux development environments. Strong communication, analytical, and problem-solving skills. Preferred Qualifications Experience with formal verification and low-power verification techniques. Exposure to SOC-level verification . Experience in cross-site collaboration and working with global teams. Job Types: Full-time, Permanent Pay: ₹1,500,000.00 - ₹3,000,000.00 per year Benefits: Health insurance Provident Fund Work Location: In person

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts – Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electronics/Electrical Engineering #LI-SR5 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AI Centre Ethernet Switching Architect India-remote. person could be based anywhere in India - Remote work will be considered for exceptional profiles Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore AI Centre Ethernet Switching Architect Position Overview We are seeking a top-notch specialist Architect with over 15 years of experience to join our team in designing and developing Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet/TCP/IP protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, UALink, Ultra Ethernet with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Define and develop the architecture of AI Datacentre Switch Fabric from ground up Performance Modelling and optimization of latency, throughput and power efficiency of switch fabric Decompose the architecture into sub blocks for implementation by design team Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control, packet spraying Apply knowledge of InfiniBand/Ultra Ethernet, NVLink/UALink, or similar protocols for feature implementation. Understanding/experience of IOS/Junos or equivalent software platform Use P4 or related languages for programmable packet processing. Working with design, software, verification team for complete product solutions Documentation of architecture and stay updated on AI networking trends. Required Qualifications Education: MS/PhD in Electrical/Electronic Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Soft Skills: Strong problem-solving, communication, and teamwork skills. Position Overview Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to achieve SoC functional and performance goals. Strong proficiency in DSP architectures, AMBA protocols, and RTL coding is required, along with proven ability to deliver high-quality designs. Preferred skills include Matlab/NumPy/C/C++, high-speed SerDes, FPGA-based validation, and post-silicon bring-up.

Role Description: A highly skilled VLSI Frontend Design Engineer with hands-on experience in architecting and developing complex SoCs from scratch. Exp: 8+ years Location: Trivandrum. Experience: 8–10 years in VLSI Frontend & RTL Design, with at least one complete end-to-end SoC development ownership. Strong RTL Design Expertise: Verilog, SystemVerilog, VHDL. Micro-architecture Design: Experience defining and implementing high-performance compute or control-intensive SoC subsystems. Interface & Protocol Knowledge: AMBA (AXI/AHB/APB), PCIe, DDR, USB, MIPI, I2C/SPI, Ethernet, etc. EDA Tools: Synopsys/Cadence/Siemens front-end tools (Design Compiler, Spyglass, VCS, Incisive, etc.). Power-aware Design Techniques: Clock gating, multi-Vt, UPF/CPF based design. Good understanding of DFT, CDC, Linting, Synthesis constraints , timing closure. Exposure to RISC-V/ARM architecture , cache design, coherency protocols, and IO subsystems. Strong documentation skills, design reviews, and collaboration in cross-functional teams. Experience with AI/ML accelerators , Automotive/ADAS SoCs, or high-speed SerDes. (Good to have) Knowledge of High-Level Synthesis (HLS) flows and SystemC modeling. Familiarity with firmware/embedded software and driver bring-up. Educational Qualification: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, VLSI, or equivalent from a reputed institute.

1. Strong coding with Verilog and SystemVerilog 2. Good knowledge of AHB,AXI, AMBA protocol, exp in Ethernet 3. Many experiences with sequence creation, functional cover groups and assertion coding. 4. Strong C/C++ software development experiences 5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby. Show more Show less

About the Role: We are seeking a highly experienced Verification Engineer to join our dynamic team, driving innovation in advanced verification methodologies for complex semiconductor designs. You will play a key role in architecting, developing, and deploying verification methodologies for industry-leading IPs and sub-systems. Key Responsibilities: Lead the deployment of verification tools, platforms, and strategies for complex IPs Drive simulation-based and hardware-assisted verification efforts, including debugging and root cause analysis Apply expertise in a broad range of verification technologies, including simulation, static, and formal verification Develop and enhance verification methodologies, including verification cockpits and CAD flows Collaborate cross-functionally with IP design and DV teams as well as tools teams to ensure product quality Mentor and guide junior engineers, fostering a culture of technical excellence Qualifications: 10+ years of experience in verification engineering for complex hardware systems Deep expertise in simulation and debug, with a proven track record of silicon success Hands-on experience with Static/ Formal verification tools and methodologies Experience developing and deploying verification methodologies, including verification cockpits and CAD flows Exposure to hardware-assisted verification environments (FPGA prototyping, emulation) is a strong plus Strong analytical, problem-solving, and communication skills Bachelors or Masters in Electrical Engineering, Computer Engineering, or related field Familiarity with industry-standard verification languages (SystemVerilog, UVM, SVA) Experience with scripting and automation (Python, Perl, TCL) Track record of technical leadership and cross-functional collaboration Why Synopsys: Join a team that powers innovation and values agility, courage, excellence, and trust. We offer opportunities to work on cutting-edge technology and make a real impact. Show more Show less

Job Overview Experience: 3 – 15 years Responsibilities Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks—defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills And Experience Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Job Title: Design Verification Engineer Experience: 10+ Company: Avecas Job Overview: We are seeking motivated Design Verification Engineers to join our VLSI team. The role involves verifying complex digital designs at block and SoC level using advanced methodologies to ensure functional correctness, quality, and performance. Key Responsibilities: Develop and execute test plans, testbenches, and verification environments . Work on SystemVerilog/UVM-based verification . Create and run directed, constrained-random, and regression tests . Debug and resolve design/verification issues using EDA tools. Collaborate with RTL design, architecture, and physical design teams. Document verification results and maintain coverage metrics. Required Skills: Strong knowledge of Digital Design and Verilog/SystemVerilog . Understanding of functional verification methodologies (UVM/OVM). Hands-on experience with EDA tools (simulation, debugging, coverage analysis). Familiarity with scripting languages (Python, Perl, TCL, Shell) is a plus. Good problem-solving, debugging, and communication skills. Nice to Have (for experienced candidates): Exposure to SoC-level verification . Knowledge of low power verification, CDC, or formal verification . Experience in industry-standard simulators and verification IPs . Why Join Us? ✅ Opportunity to work on cutting-edge SoC/ASIC projects . ✅ Collaborative and learning-driven environment. ✅ Growth opportunities in the VLSI design & verification domain.

Job Requirements Job Title: Senior Design Verification Engineer We are currently seeking a Senior Design Verification Engineer to join our team on a temporary basis. As a key member of our engineering team, you will be responsible for verifying and validating complex digital designs to ensure they meet the highest quality standards. Key Responsibilities: Develop and execute verification plans for digital designs Write test benches and test cases to verify functionality Collaborate with design engineers to identify and resolve issues Analyze and debug failures to improve design quality Stay current on industry trends and best practices in design verification Qualifications: Bachelor's degree in Electrical Engineering or related field Proven experience in design verification of digital designs Proficiency in Verilog/SystemVerilog and UVM methodology Strong problem-solving skills and attention to detail Excellent communication and teamwork abilities If you are a talented Design Verification Engineer looking to make an impact in a dynamic and innovative environment, we would love to hear from you. Apply now to join our team!

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements Preferred Experience Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts - Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. Academic Credentials Bachelors or Masters degree in computer engineering/Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 4 years of experience with verification methodology such as Universal verification methodology (UVM). 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc. Experience with SystemVerilog, SVA, and functional coverage. Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience with industry-standard simulators, revision control systems, and regression systems. Experience with the full verification life cycle. Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units. Excellent problem solving and communication skills. About The Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Measure to identify verification holes and to show progress towards tape-out. Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Minimum qualifications: Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience. 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture. Experience in ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master’s degree in Electrical/Computer Engineering. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Experience with methodologies for low power estimation, timing closure, synthesis. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of our platform IP team, you will be a part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis to specify and deliver RTL. You will solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance and power. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. Perform RTL development (SystemVerilog), debug functional/performance simulations. Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Bangalore,Karnataka,India Job ID 768636 About Us We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What we offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. If you are passionate about ASIC IP verification engineering and eager to contribute to cutting-edge projects in a global setting, we encourage you to apply. Key Responsibilities: Take part of the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 10+ years industry experience in ASIC IP verification using SystemVerilog and UVM. Strong experience in / with: Development of verification test plans and create directed/randomized test cases. Formal verification. In implementing scoreboards, checkers, bus functional models in existing testbench environment. AMBA-based designs such as AXI and CHI. SystemVerilog Assertions. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: ARM-based real-time embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Join our Team About this opportunity: The Developer role at Ericsson is a multifaceted position encompassing a broad range of responsibilities, from requirement analysis and system design, through to product documentation and PLM support. Our developers are instrumental in the creation and maintenance of various components, systems, and solutions within our product portfolio. Collaborating in accordance with the Ericsson Product Development Principles, our developers are champions of innovation, utilizing their unique skill sets across all stages of the development lifecycle. Ericsson presents an exciting platform to showcase your expertise and foster professional growth. This robust role promises diverse tasks and great influence in shaping our technology solutions. To about the specific governance and responsibilities, please follow this read more What you will do: Actively participate in all development activities, such as requirement analysis, system, architecture, hardware and software design. Collaborate in the integration, verification, and simulation processes for optimal product development. Contribute to the designing of tools and support for Product Lifecycle Management (PLM). Play a role in creating comprehensive product documentation. Adhere to Ericsson's Product Development Principles throughout the development process. Take on additional responsibilities and duties as detailed in the position-specific . The skills you bring: CEE10 Design DGS. SDI3 Upgrade. SDI3 Solution Design. Knowledge Sharing and Collaboration Skills. SDI3 Integration. GDCE. Coaching and Mentoring. Innovation and Creativity. Google GCP. AWS Public Cloud. Azure Public Cloud. AWS Outpost. Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

The people are the culture. We encourage a culture of passion for technology solutions that impact businesses. We also make sure that our people pursue their individual passions. Working with us means you get an in-depth understanding of a range of industries and emerging technologies that help us build solutions that are futuristic and impactful. More importantly, the experience of being at MarvyLogic may help you evolve as a person toward enjoying a more fulfilling life. Minimum BE/BS degree in Electrical/Electronics/Computer science required. At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts. Experience in physical layer ASIC architecture, micro-architecture development, design and debug. Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog. Experience with lint, synthesis, CDC, STA, formality, ECO process, tool flows, and scripting. Knowledge in one or more of the following areas, a definite plus: Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer), DSP fundamentals/Filter/FFT design/Datapath design/Error Control Coding, Computer architecture/Processor fundamentals. Preferred Qualifications: Strong knowledge of ASIC design methodologies and flows. Ability to proactively take on responsibilities and competent to work in a start-up environment. Worked with product development companies and having seen at least a couple of tape-outs. Experience with silicon bring-up in the lab and debugging is a definite plus. Experience with FPGA realizations of higher complexity designs. Ability to work with teams spread across geography with excellent communication skills. Responsibilities: Develop key blocks of logic in a next-generation physical layer/mixed signal SOCs. Perform hardware feasibility analysis and come up with a micro-architecture specification helping it map to a high performance, implementable design. Work with verification, DFT, synthesis, circuits, backend implementation teams to realize quality implementation.,

Hi All, Greetings' from Eximietas Design....! We are Hiring ASIC SOC RTL Design Engineer/Leads. Job Title: ASIC SOC RTL Design Engineer/Leads ..! Experience: 8+ Years. Location: Visakhapatnam or Bangalore. Job Description: Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a critical role in defining and implementing the microarchitecture of cutting-edge semiconductor designs. You will work on complex RTL design challenges, collaborate with cross-functional teams, and contribute to the delivery of high-performance, power-efficient, and innovative solutions. Key Responsibilities: Define and develop microarchitecture specifications for complex SoC designs. Lead RTL design and implementation using Verilog/SystemVerilog, ensuring optimal performance, power, and area (PPA). Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution. Perform design trade-off analysis to meet functional, performance, and power requirements. Develop and implement design methodologies to improve efficiency and quality. Mentor and guide junior engineers, fostering a culture of innovation and excellence. Participate in design reviews, provide technical leadership, and ensure adherence to project timelines. Qualifications: 8+ years of hands-on experience in RTL design and microarchitecture development. Strong expertise in RTL design using Verilog/SystemVerilog and logic synthesis . Proficiency in microarchitecture design for complex SoCs, including pipelining, caching, and memory subsystems . Experience with low-power design techniques (e.g., clock gating, power gating, multi-Vt optimization). Familiarity with advanced process nodes and their specific challenges (e.g., finFET, multi-patterning). Strong scripting skills in Tcl, Python, or Perl for automation and flow development. Excellent problem-solving skills and attention to detail. Strong communication and leadership skills. What We Offer: Opportunity to work on cutting-edge semiconductor designs and innovative technologies. Collaborative and inclusive work environment. Competitive compensation and benefits package. Professional growth and development opportunities. Interested Engineers please share your updated resume : maruthiprasad.e@eximietas.design

Bangalore, India • Full Time Meta Infrastructure Engineering Hardware Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Design Verification Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Track record of 'first-pass success' in ASIC (Application-Specific Integrated Circuit) development cycles 5+ years of experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification 5+ years experience in IP/sub-system and/or SoC (System on Chip) level verification based on SystemVerilog UVM and OVM (Open Verification Methodology) based methodologies Experience in one or more of the following areas along with functional verification - System Verilog Assertions, Formal, Emulation Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Preferred Qualifications 8+ years of experience in development of UVM based verification environments from scratch Experience in IP, sub-system and SoC level verification using SystemVerilog, UVM Experience with IP or integration verification of high-speed interfaces like AMBA, PCIe (Peripheral Component Interconnect Express), DDR (Double Data Rate), Ethernet Experience with verification of ARM/RISC-V based sub-systems or SoC (Systems on Chip) Experience with Design verification of Data-center applications like Video, Artificial Intelligence/Machine Learning (AI/ML) and Networking designs Experience with revision control systems like Mercurial, Git or SVN Experience working across and building relationships with cross-functional design, model and emulation teams About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Bangalore, India • Full Time Meta Infrastructure Engineering Hardware Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Verification Engineer, Formal Responsibilities Provide technical leadership in Formal Verification Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level Work with Architecture and Design teams to come up with Formal Verification specification and implementation Define Formal Verification scope, create Formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level Build reusable/scalable environments for Formal Verification and deploying tools Evaluate and recommend EDA solutions for Formal Verification Provide training for internal teams and mentoring engineers related to Formal Verification Technology Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 5+ years of experience in Formal Verification Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc Experience with Formal Verification methodologies, complexity reduction techniques and abstraction techniques Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Fluency in hardware description languages, such as SystemVerilog and SVA Proficiency in scripting languages such as Python, Perl, or Tcl Experience with JasperGold or VC-Formal Preferred Qualifications 8+ years of experience in Formal Verification Experience to quickly understand and interpret specifications and extract design behaviors/properties Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators Experience with complex SoCs Formal verification experience in clock domain crossing, IP-XACT based register verification and low power Experience with development of fully automated flows from specification to fully verified designs Experience with simulators and waveform debugging tools About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Job Title: Principle CPU Design Verification Engineer 📍Location: Pune Experience: 9+ years 📅Work Type: Full-Time | On-Site If Interested, Please share a copy of your resume at juhi@sfconsults.com Description: We are seeking an experienced verification engineer to lead verification efforts of complex CPU and related subsystems based on the open-source RISC-V architecture. The right candidate will have deep technical expertise combined with exceptional leadership skills Responsibilities : Lead end-to-end verification from complex CPU sub-units up to CPU clusters, partnering with architecture and design teams. Develop verification infrastructure components including test-benches, scoreboard and stimulus generators. Develop and execute comprehensive verification plans for units and features Implement functional coverage models. Debug designs in simulation, prototyping platforms and silicon. Continuously drive methodology improvements to improve efficiency. Lead senior and junior engineers as a team to accomplish successful projects. Skills & Qualification Required: SystemVerilog verification development experience Testbench construction using UVM or analogus methodology. Scoreboards and stimulus generators for complex units. Strong background in one or more common CPU ISAs. x86, ARM, MIPS, RISC-V etc. Strong background in processor coherency and MP programming Project ownership throughout the project lifecycle. Demonstrated team leadership experience with outstanding communication skills. Highly motivated self-starter with strong execution mindset and collaborative approach Post-silicon debug-experience strongly preferred. #wearehiring #applynow #jobalert #verificationengineer

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR, PCIe, USB, or HBM. Your expertise extends beyond individual contributionyou are equally comfortable leading and mentoring small teams, fostering an environment of collaboration and shared learning. You are adept at translating functional specifications into detailed micro-architecture and design documents, always ensuring clarity and precision. Your technical toolkit includes mastery of Verilog/SystemVerilog, and you are well-versed in industry-standard flows encompassing linting, CDC analysis, synthesis, and static timing. Youre not just a technical expert; you are a proactive communicator, an enthusiastic collaborator, and a natural problem solver who takes initiative and ownership of deliverables. Your ability to adapt to a global, multi-site team environment is matched only by your commitment to continuous learning and professional growth. If youre ready to take on a pivotal role in shaping next-generation silicon IP, Synopsys is where your aspirations and impact can soar. What Youll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores. Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features. Contributing as an individual designerhandling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development. Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing. Leading or mentoring small teams of designers, providing technical guidance and fostering professional development. Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies. Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables. The Impact You Will Have: Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide. Elevating Synopsys reputation for technical excellence and innovation in the IP design space. Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies. Enabling customers to achieve faster time-to-market and superior silicon performance. Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth. Driving continuous improvement in design methodologies, enhancing efficiency and product quality. Supporting Synopsys mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions. What Youll Need: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or related discipline. 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM. In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design. Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification. Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces). Familiarity with scripting languages such as Perl or Shellan advantage. Demonstrated ability to technically lead or mentor small teams of engineers. Who You Are: A collaborative team player who thrives in a multi-site, multicultural environment. An effective communicator, able to translate complex technical concepts for diverse audiences. A proactive problem-solver with strong analytical and troubleshooting skills. Self-motivated, showing high initiative and ownership of responsibilities. Adaptable and eager to learn, always seeking opportunities for personal and professional growth. Committed to fostering a positive, inclusive, and innovative team culture. The Team Youll Be A Part Of: You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores. As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design. The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Principal Software Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each otherevery day. Experience And Technical Skills Required 5+ to 12 years of hands-on experience in Software development experience with object-oriented languages (C++, Java, Python, etc.) in an industrial setting Strong fundamental knowledge in designing data structures, algorithms, and software engineering principles Strong experience in C/C++ development Strong experience in Java development Excellent verbal and written communications skills Strong problem solving and analytical skills Advantage Knowledge/Experience with IP-XACT Knowledge/Experience with SystemVerilog and/or UVM Knowledge/Experience of communication protocols such as USB/AMBA/Ethernet Qualifications BE/BTech or ME/M.Tech Graduate with Computer Science/Electronics & Communication/Electrical & Electronics/VLSI engineering or any other equivalent courses Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore whats possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity Were doing work that matters. Help us solve what others cant. Show more Show less