675 Systemverilog Jobs - Page 3

Alternate Job Titles: Verification Architect We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a visionary and highly experienced engineering professional, passionate about verification and digital design methodologies. With at least 15 years of solid experience in IP and SoC verification, you have consistently demonstrated technical excellence and leadership in your career. You thrive in challenging environments and are adept at architecting robust verification infrastructures from the ground up, particularly within the EDA ecosystem. You possess deep hands-on knowledge of industry-leading tools such as Synopsys VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. Your expertise enables you to design unified reference flows and scalable methodologies that empower teams and accelerate project success. You excel at independently owning and delivering on complex assignments, while also being a collaborative team player who enjoys mentoring and elevating junior engineers. Your communication skills are outstanding, allowing you to articulate technical concepts to diverse audiences and influence cross-functional teams. You have a proven ability to multi-task, manage priorities, and drive technical initiatives with a strategic mindset. Your academic foundation includes a bachelor’s degree in electronics, electrical, or computer engineering, and you continuously seek to expand your knowledge and impact in the field of digital IP verification. You are ready to take on a leadership role, shaping methodology and best practices for the next generation of high-performance silicon designs. What You’ll Be Doing: Architecting and implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects. Partnering with global engineering teams to define, document, and propagate best-in-class verification methodologies and standards. Leading and mentoring junior engineers, fostering a culture of technical growth, innovation, and collaboration within the team. Driving technical initiatives and independently managing high-impact assignments, ensuring timely and high-quality deliverables. Collaborating closely with tool development teams to influence product evolution and optimize verification workflows for maximum efficiency. Supporting customers and internal stakeholders by troubleshooting, optimizing, and refining verification processes and flows. The Impact You Will Have: Elevate Synopsys’ digital IP verification capabilities by delivering robust, unified, and scalable methodology solutions. Accelerate time-to-market for high-performance silicon products by streamlining and standardizing verification processes. Empower global verification teams with best-in-class flows, tools, and practices, driving consistent project success. Shape the verification strategy for next-generation Synopsys IP and SoC offerings, directly influencing product quality and customer satisfaction. Mentor and develop the next wave of verification engineers, fostering a culture of learning and technical excellence. Contribute to the evolution of Synopsys’ EDA tool ecosystem by providing critical feedback and championing innovative solutions. Enhance Synopsys’ leadership position in the semiconductor industry through continuous improvement and adoption of cutting-edge verification methodologies. What You’ll Need: Minimum 15 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership. Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. Demonstrated ability to architect and implement verification flows and infrastructure for complex digital designs. Solid programming and scripting skills (SystemVerilog, UVM, Tcl, Python or similar languages). Bachelor’s degree in electronics, electrical, or computer engineering (advanced degrees a plus). Experience with multi-tasking and managing technical projects independently. Ability to document, communicate, and propagate technical methodologies across global teams. Who You Are: Innovative problem solver who thrives in dynamic, fast-paced environments. Excellent communicator, able to distill complex technical topics for diverse audiences. Natural mentor and team player, passionate about knowledge-sharing and team development. Strategic thinker with a keen eye for detail and a commitment to quality. Self-motivated leader who takes initiative and drives projects to successful completion. Adaptable, resilient, and eager to learn and grow alongside industry leaders. The Team You’ll Be A Part Of: You will be a core member of the newly established Digital IP Verification Methodology (COE) team, a group of forward-thinking engineers dedicated to advancing verification excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. Together, you will shape the future of digital IP verification, enabling Synopsys and its customers to deliver world-class silicon solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement. What You’ll Be Doing: Designing and implementing verification environments to ensure the correctness of Interface IP protocols. Creating and executing detailed test plans to verify complex ASIC designs. Developing and maintaining verification IP and testbenches using SystemVerilog and UVM. Collaborating with design and architecture teams to identify and fix bugs. Performing functional coverage analysis and driving coverage closure. Staying current with the latest verification methodologies and tools to continually improve processes. Mentoring and guiding junior verification engineers in best practices and methodologies. The Impact You Will Have: Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications. Enhancing the robustness and efficiency of our verification processes and methodologies. Contributing to the successful launch of Interface IP products, impacting various industries. Driving innovation and excellence within the verification team. Improving the overall performance and functionality of Synopsys' IP offerings. Fostering a culture of continuous improvement and technical excellence. What You’ll Need: Extensive experience in ASIC digital verification, specifically with Interface IP protocols. Proficiency in SystemVerilog and UVM methodologies. Strong understanding of digital design and verification concepts. Experience with simulation tools such as VCS, ModelSim, or similar. Excellent problem-solving skills and attention to detail. Who You Are: Detail-oriented with a strong analytical mindset. Excellent communicator, able to convey complex technical concepts clearly. Collaborative team player who thrives in a dynamic environment. Proactive and self-motivated, with a commitment to continuous learning. Mentor and leader, capable of guiding and developing junior engineers. The Team You’ll Be A Part Of: You will join a dedicated team of engineers focused on the design and verification of high-performance digital IPs. Our team is committed to innovation, quality, and excellence, working collaboratively to push the boundaries of technology. We value continuous learning and professional growth, providing ample opportunities for development and advancement.

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are one of 49 US AI startups that have raised $100M or more in 2024 We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal / Staff Physical design Engineers Bangalore Founded in 2023,by Industry veterans HQ in California,US Location: Greater Bengaluru Area Company Description We are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI. Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision. Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision. Physical Design Engineers Experience in Physical Design implementation (from RTL to GDS) at Block or SoC designs on advanced process nodes Expertise and experience with industry-standard CAD tools from Synopsys, Cadence or Siemens. Experience in collaborating with RTL design and Flows teams to drive feasibility studies and converge Block/SoC designs to meet target power, frequency, and area targets. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE/MSEE 5-15 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Design Verification Engineer (India) Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background We are among 49 US AI startups that have raised $100M or more in 2024 We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing. Roles and Responsibilities Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage. Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device. Define and implement infrastructure for effective HW/SW co-simulation. Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements. The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms. Skills/Qualifications Proven industry experience and successful track record in verifying chip- and block-level RTL designs in one or more of these PCIE Gen4 /Gen5 /Gen6 CXL for high-performance networking or computing chips DPUs, accelerators, Deep experience with full chip verification and infrastructure development. Strong current knowledge of UVM constructs, components, and practices. Expert knowledge of SystemVerilog, as well as Python or other scripting languages. Experience with C/C++ and general software engineering principles is highly desirable. Minimum BSEE/CE + 12-17years or MSEE/CE + 10-16 years experience. Proven track record of design execution and quality on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior Principal Design Verification Engineer (India)/ Principal Design Verification Engineer Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background We are one among 49 US AI startups that have raised $100M or more in 2024 We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing. Roles and Responsibilities Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage. Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device. Define and implement infrastructure for effective HW/SW co-simulation. Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements. The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms. Skills/Qualification Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips, such as Network Interface Controllers, Smart-NICs, DPUs, accelerators, and/or switches in advanced silicon geometries. PCIe5 /PCIe6-Transcation layer Deep experience with full chip verification and infrastructure development. Strong current knowledge of UVM constructs, components, and practices. Expert knowledge of SystemVerilog, as well as Python or other scripting languages. Experience with C/C++ and general software engineering principles is highly desirable. Minimum BSEE/CE + 12-20 years or MSEE/CE + 10-18 years experience. Proven track record of design execution and quality on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

As an ASIC Verification Lead at Eviden, a global leader in data-driven digital transformation, you will play a key role in integrating the ASIC functional verification team. The ASICs developed by Eviden include network controllers, routers, and cache coherence controllers for high-end and high-performance servers. Your expertise will be instrumental in utilizing Constraint-Random, Coverage Driven functional verification methodologies within the UVM verification framework to ensure thorough verification of complex ASIC designs. Your main responsibilities will include acquiring in-depth knowledge of ASIC architecture and microarchitecture by studying specifications and collaborating with architecture and logical design teams. You will actively participate in defining verification strategies and methodologies, developing simulation environments, and maintaining verification specifications. Collaborating closely with the logical design team, you will write and execute test plans, develop coverage models, and verification environments using UVM-SystemVerilog/C++. Furthermore, you will be responsible for monitoring, analyzing, and debugging simulation errors, as well as assessing simulation coverage results to enhance tests and meet coverage targets efficiently. Your role will also involve providing recommendations on tools and methodologies to enhance productivity, along with mentoring junior engineers to ensure maintainable and reusable code across projects. To excel in this role, you should have a proven track record of successful verification of complex SoCs or ASICs and a strong command of UVM or equivalent verification methodologies. Proficiency in developing Constraint-Random/Coverage-Driven verification environments in SystemVerilog/C++ is essential, along with expertise in simulation tools and coverage database visualization tools. Your ability to develop effective test plans, swiftly identify functional defects, and implement solutions under tight deadlines will be crucial. The ideal candidate will have a minimum of 7 years of experience and hold a Master's or Engineer's degree in Electronics and Communication Engineering. If you are passionate about driving innovation in ASIC verification and possess strong problem-solving skills, we invite you to join our dynamic team at Eviden and contribute to shaping the future of digital transformation. Let's grow together at Eviden.,

As an ASIC Verification Engineer at our game-changing AI solutions company, you will be responsible for developing verification environments for modules, subsystems, top level, and FPGA. You will build models, checkers, and random test frameworks using SystemVerilog and UVM. Additionally, you will participate in Low power analysis (UPF), power estimation, and C modeling. Your role will also involve performing lint, CDC, code coverage, and functional coverage, as well as formal verification of modules using SVA assertions. To excel in this role, you should have experience in verifying complex subsystems and ASICs. You should be adept at building scalable verification environments from scratch and proficient in Verilog, UVM, EDA tools, scripting, automation, build, and regression systems. Exposure to FPGA emulation platforms, silicon bringup, and board debug will be beneficial for this position. A degree in BTech/MTech in EE/CS with any level of experience is required to be considered for this opportunity. If you are passionate about pushing the boundaries of AI technology and want to be a part of the edge AI revolution, we look forward to hearing from you. Please reach out to us at +91-9071106778 to explore this exciting opportunity further.,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Were building high-performance RISC-V CPUs from the ground up, and we need someone who can help us test them thoroughly and thoughtfully. As a testbench lead, you&aposll design and maintain the infrastructure that makes sure our cores behave exactly as intended. If you enjoy figuring out how things break (and fixing them), building clean and reusable systems, and working with a team that values both rigor and creativity, wed love to talk. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Youve built and maintained testbenches for CPU cores or similar designs, using SystemVerilog, UVM, and C++. You like creating clean, reusable components from transactors to functional models that others can plug in and build on. Youre comfortable working across both software-style C++/UVM environments and hardware-style simulation flows. You enjoy collaborating with design teams and helping them debug issues quickly and clearly. What We Need Someone to design and grow a UVM testbench setup that works for both block-level and full-chip simulation. The ability to write C++ code that fits into a DV framework and help shape that framework as it evolves. A good understanding of CPU microarchitecture and how to test it effectively. Comfort working across tools, from open-source simulators like Verilator to commercial environments and emulators. What You Will Learn How to design testbenches that scale with complexity and keep them maintainable as the chip grows. How to support both simulation and emulation from the same DV infrastructure. How custom C++ and UVM environments can coexist to improve verification workflows. How different teams RTL, DV, software, tools etc come together to build AI-focused silicon. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to?U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information?and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. Show more Show less

You will be responsible for designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. This includes designing and implementing RTL for DFT IP, including POST and IST. Additionally, you will be developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Your role will also involve owning, maintaining, extending, and enhancing existing DFT IP like LBIST. At Cadence, we are focused on hiring and developing leaders and innovators who are passionate about making an impact on the world of technology. Join us in our mission to solve challenges that others cannot.,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated graduate in Electronics Engineering, ready to launch your career in the semiconductor industry. With internship or project experience in digital design or verification, you bring a strong academic foundation and a passion for technology. You thrive in collaborative, multicultural teams, value open communication, and are committed to continuous learning. You pay attention to detail, enjoy solving problems, and adapt quickly to new tools and methodologies. Proactive and eager, you are excited to make a real impact while growing in a supportive, inclusive environment where your ideas are valued. What Youll Be Doing: Collaborating with experienced engineers to develop and deliver high-quality verification solutions for advanced semiconductor projects. Applying your knowledge in Verilog, SystemVerilog, and UVM to support verification and design validation tasks. Assisting in the development and maintenance of testbenches, scripts, and automation flows to improve verification efficiency and coverage. Participating in technical reviews and supporting the creation of test plans and testcases for key protocols such as PCIe. Analyzing, debugging, and resolving design issues in partnership with global teams. Engaging in team knowledge-sharing sessions and ongoing training to stay current with evolving verification methodologies and Synopsys technologies. The Impact You Will Have: Enable Synopsys customers to achieve first-time silicon success through robust verification and support. Enhance the quality, reliability, and performance of next-generation semiconductor products. Contribute to the development of scalable and reusable verification environments. Drive customer satisfaction by assisting in timely and effective technical solutions. What Youll Need: Bachelors or Masters degree in Electronics Engineering or a related field. Internship or project experience in digital design or verification. Proficiency in Verilog and SystemVerilog; exposure to UVM is a plus. Familiarity with scripting languages (Python, TCL, Shell) is beneficial. Strong analytical and debugging skills to resolve technical issues efficiently. Who You Are: Clear and confident communicator, able to convey complex ideas effectively. Collaborative team player with a positive attitude and a willingness to learn. Detail-oriented and organized, able to manage multiple priorities. Proactive, adaptable, and open to feedback and challenges. The Team Youll Be A Part Of: You will be a valued member of a dynamic Verification IP (VIP) team focused on delivering state-of-the-art solutions for Synopsys semiconductor customers. The team works closely with R&D, product management, and customer support to ensure seamless integration and customer success. Together, youll innovate, share knowledge, and advance industry-leading technologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers specifications, whether theyre a major telecom organization or automotive company, etc. What You Can Expect Individual contribution for the block, SoC, and subsystem-level verification. Develop a test bench, test plan, and design a verification environment at the block and full chip levels. Technically, lead junior engineers. What We&aposre Looking For Must have a good digital logic and the fundamentals of digital design verification. The candidate must have excellent skills in digital logic verification and hardware description language Must have worked on SoC, subsystem-level verification. Knowledge in object-oriented programming using languages such as SystemVerilog and UVM methodology is an added advantage. Must be familiar with verification test planning, test execution, and sign-off for the verification activity. Must have good experience in using simulation tools and proficiency in simulation debug techniques. Strong knowledge/experience in building the verification environment. Must have hands-on knowledge of test-bench development and automation, bug tracking, and regression mechanisms Should be able to act as the team lead to determine methods and procedures for new assignments and coordinate activities of other team members to ensure successful project completion. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what its like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

Principal / Staff Design Verification Engineer Bangalore Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they're looking for passionate individuals to join a seasoned and dynamic team. Positions Available in Bengaluru, India/fully onsite Principal Design Verification engineer Responsibilities​: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc.​ Qualifications and Preferred Skills​ BS, MS in Electrical Engineering, Computer Engineering or Computer Science 6-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs Experience with formal verification techniques, emulation platforms is a plus Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com

Senior Staff Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) Company Background We are among 49 US AI startups that have raised $100M or more in 2024 We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 10 years or MSEE/CE + 8 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Design Verification Engineer (India) Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background We are among 49 US AI startups that have raised $100M or more in 2024 We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing. Roles and Responsibilities Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage. Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device. Define and implement infrastructure for effective HW/SW co-simulation. Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements. The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms. Skills/Qualifications Proven industry experience and successful track record in verifying chip- and block-level RTL designs in one or more of these PCIE Gen4 /Gen5 /Gen6 CXL for high-performance networking or computing chips DPUs, accelerators, Deep experience with full chip verification and infrastructure development. Strong current knowledge of UVM constructs, components, and practices. Expert knowledge of SystemVerilog, as well as Python or other scripting languages. Experience with C/C++ and general software engineering principles is highly desirable. Minimum BSEE/CE + 12-17years or MSEE/CE + 10-16 years experience. Proven track record of design execution and quality on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

AI Centre Ethernet Switching Architect India-remote. person could be based anywhere in India - Remote work will be considered for exceptional profiles Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore AI Centre Ethernet Switching Architect Position Overview We are seeking a top-notch specialist Architect with over 20 years of experience to join our team in designing and developing Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet/TCP/IP protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, UALink, Ultra Ethernet with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Define and develop the architecture of AI Datacentre Switch Fabric from ground up Performance Modelling and optimization of latency, throughput and power efficiency of switch fabric Decompose the architecture into sub blocks for implementation by design team Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control, packet spraying Apply knowledge of InfiniBand/Ultra Ethernet, NVLink/UALink, or similar protocols for feature implementation. Understanding/experience of IOS/Junos or equivalent software platform Use P4 or related languages for programmable packet processing. Working with design, software, verification team for complete product solutions Documentation of architecture and stay updated on AI networking trends. Required Qualifications Education: MS/PhD in Electrical/Electronic Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Soft Skills: Strong problem-solving, communication, and teamwork skills. Position Overview Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications. What You Can Expect Develop the architecture for a functional verification environment, including reference models, bus-functional monitors, and drivers Contribute to the development methodology and extend RoCE-related learnings within the team Write comprehensive verification test plans using random techniques and coverage analysis, in collaboration with design teams Develop test cases and tune the environment to meet coverage goals; debug failures and work with designers to resolve issues Verify boot code and architect, develop, and maintain tools to streamline the design of advanced multi-core SoCs Translate engineering requirements into scalable and user-friendly software tools optimized for highly parallel compute environments Perform unit and regression testing of developed software tools What We're Looking For BS in Computer Engineering, Electrical Engineering, or Computer Science with 15+ years of verification or design experience, or MS/PhD with 10+ years of experience Hands-on expertise in RoCE (RDMA over Converged Ethernet) Strong experience with SystemVerilog and UVM Proven ability to write detailed test plans and develop sophisticated directed and random verification environments Proficiency in scripting languages such as Python or Perl, and familiarity with EDA verification tools Experience with object-oriented design and implementation Good understanding of Linux operating systems Solid programming skills, especially in C++ and ARM assembly Working knowledge of high-speed Ethernet Understanding of other networking protocols is a plus Diligent, detail-oriented, and proactive, with the ability to manage tasks independently Open to feedback and able to work with diverse perspectives Flexible and adaptable; quick to learn in a fast-paced environment Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated graduate in Electronics Engineering, ready to launch your career in the semiconductor industry. With internship or project experience in digital design or verification, you bring a strong academic foundation and a passion for technology. You thrive in collaborative, multicultural teams, value open communication, and are committed to continuous learning. You pay attention to detail, enjoy solving problems, and adapt quickly to new tools and methodologies. Proactive and eager, you are excited to make a real impact while growing in a supportive, inclusive environment where your ideas are valued. What You’ll Be Doing: Collaborating with experienced engineers to develop and deliver high-quality verification solutions for advanced semiconductor projects. Applying your knowledge in Verilog, SystemVerilog, and UVM to support verification and design validation tasks. Assisting in the development and maintenance of testbenches, scripts, and automation flows to improve verification efficiency and coverage. Participating in technical reviews and supporting the creation of test plans and testcases for key protocols such as PCIe. Analyzing, debugging, and resolving design issues in partnership with global teams. Engaging in team knowledge-sharing sessions and ongoing training to stay current with evolving verification methodologies and Synopsys technologies. The Impact You Will Have: Enable Synopsys’ customers to achieve first-time silicon success through robust verification and support. Enhance the quality, reliability, and performance of next-generation semiconductor products. Contribute to the development of scalable and reusable verification environments. Drive customer satisfaction by assisting in timely and effective technical solutions. What You’ll Need: Bachelor’s or Master’s degree in Electronics Engineering or a related field. Internship or project experience in digital design or verification. Proficiency in Verilog and SystemVerilog; exposure to UVM is a plus. Familiarity with scripting languages (Python, TCL, Shell) is beneficial. Strong analytical and debugging skills to resolve technical issues efficiently. Who You Are: Clear and confident communicator, able to convey complex ideas effectively. Collaborative team player with a positive attitude and a willingness to learn. Detail-oriented and organized, able to manage multiple priorities. Proactive, adaptable, and open to feedback and challenges. The Team You’ll Be A Part Of: You will be a valued member of a dynamic Verification IP (VIP) team focused on delivering state-of-the-art solutions for Synopsys’ semiconductor customers. The team works closely with R&D, product management, and customer support to ensure seamless integration and customer success. Together, you’ll innovate, share knowledge, and advance industry-leading technologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Hyderabad /Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A US based well-funded product-based startup looking for Highly talented Senior Physical Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad /Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semi&aposs expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic Design Verification Engineer to join our fun and dynamic team of experienced innovators. What you&aposll do: Own the end-to-end verification of new customer features Review design specifications and devise verification plans Build testbenches and analyze test failures to uncover design bugs Facilitate bit-matching of RTL design and MATLAB system models Integrate 3rd party VIPs for compliance testing of standard protocols Build releases of our design IP for customers Support post-silicon validation and bring-up activities Take on opportunities to lead, plan, and coordinate tasks with team members Collaborate closely with Design, Systems, Analog, FW, and PD teams Contribute to the continuous improvement of verification methodologies and processes What you&aposll need: 5+ years of ASIC design verification experience An applied understanding of UVM and verification techniques Experience with constrained-random verification in SystemVerilog and UVM Formal Verification, and Power-aware UPF verification techniques Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make Verification experience in SerDes PHY, DSP, and Analog mixed signal is desirable Knowledge in Ethernet and PCIe standards is desirable '&aposWe have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semi&aposs expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic Design Verification Engineer to join our fun and dynamic team of experienced innovators. What you&aposll do: Own the end-to-end verification of new customer features Review design specifications and devise verification plans Build testbenches and analyze test failures to uncover design bugs Facilitate bit-matching of RTL design and MATLAB system models Integrate 3rd party VIPs for compliance testing of standard protocols Build releases of our design IP for customers Support post-silicon validation and bring-up activities Take on opportunities to lead, plan, and coordinate tasks with team members Collaborate closely with Design, Systems, Analog, FW, and PD teams Contribute to the continuous improvement of verification methodologies and processes What you&aposll need: 5+ years of ASIC design verification experience An applied understanding of UVM and verification techniques Experience with constrained-random verification in SystemVerilog and UVM Formal Verification, and Power-aware UPF verification techniques Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make Verification experience in SerDes PHY, DSP, and Analog mixed signal is desirable Knowledge in Ethernet and PCIe standards is desirable '&aposWe have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, weve got quite a lot to offer. How about you Position Overview Siemens EDA is looking for a highly motivated Product Engineer to help define, promote, and deploy hardware assisted acceleration with Veloce emulation and prototyping solutions at leading edge semiconductor and systems customers. As a hardware-assisted verification solutions expert you will be part of the world-wide Veloce experts team working with emulation and prototyping solutions for pre and post silicon validation, verification and software bring-up of industrys most complex SoC and FPGA designs using the latest advances in co-emulation technologies with Veloce Transactor Layer (VTL) transactors and testbenches. Key responsibilities Assist applications engineers (AEs) and customers with integration and debug of verification solutions to enable Testbench acceleration in a hardware-assisted verification environment Support PCIe, AMBA-based, UART, and serial protocol (SPI, I2C, ) transactors targeting emulation and prototype platforms. Build or support example designs for solutions that use SystemC or UVM transactors. Drive Veloce technology at various customers using hands-on technical expertise. Requires working directly with customers to ensure technical results are met. Promote technical customer service to build and improve customer relationships, ensuring long term customer happiness. Work closely with the sales team in a focused strategy to expand our business. Provide feedback and product ideas to our solutions product development teams. Troubleshoot and remove technical obstacles. Work very closely with all team member to ensure full customer happiness. Develop and deliver technical presentations/trainings on new features and product updates. Communicate customers' technical requirements to product marketing. Develop a network of technical relationships at a peer-to-peer level with our customers. Use complex design and tooling tasks involving multiple design environments. Cogently communicate software problems to product development. Assists other specialists in the design, development, and implementation of large-scale solutions on multiple software products and hardware platforms. Provides business and technical feedback to software and hardware vendors. Use advanced data exchange methodologies to facilitate effective data sharing between dissimilar systems or applications that span across engineering disciplines. Responsible for in-depth technical papers and presentations to customer management or at technical conferences. Guide junior engineers. Work with minimal direction on complex projects with latitude for independent judgment and discretion. Well skilled with broad proficiency. Required Qualifications We seek a graduate (Bachelor&aposs) with 5+ years of related experience or post graduate (Master&aposs) with 3+ years of proven track record. Familiarity with Verilog/SystemVerilog or SystemC and UVM Must have experience with emulation of large scale CPU, GPU or Systems-on-Chip (MPSoC) designs, emulation technologies, usages and industry approaches. Prior experience in a customer facing function such as application engineer from an emulation or prototype systems provider a plus! We&aposve got a lot to offer, how about you We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We&aposre dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Show more Show less

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We&aposre dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #DVT Show more Show less

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"