ASIC VERIFICATION ENGINEER

What You Can Expect -

• Work on Latest cutting edge CSG Switches.
• To be part of the team working on defining many Firsts for the AI Network Infrastructure Ecosystem.
• Develop and maintain verification Environment in Mix of SV/UVM.
• Understanding of the End to End spec along with Network & System topology.
• Closely working with Arch/uArch/Design team for Test Plan development and closure of the feature set across Blocks/Top level.
• Coverage Closures, Gate Level Simulations along with end to end verification cycle.
  

What We Are Looking For -

• Bachelor's/Masters/PhD with Verification experience of 8+ years
• Wide exposure to chip level (SoC) verification and SystemVerilog/UVM methodology a MUST
• Exposure to any one of the scripting languages - Perl or Python or SED/Awk
• Expertise in Co-Simulations (HW/SW) Flow and debugs
• Knowledge of networking protocols(L2/L3/L4, 1588TS, UEC) desired but not necessary.
• Expertise in the High Speed bus protocols desired - PCIe, Ethernet, AXI4.0
• Exposure the Chip level Interconnect/Testability Functions - JTAG, I2C, PLLs etc
• Experience in GLS, Coverage Driven Methodology, ATE
• Good exposure in Simulation tool usage for simulation (VCS) and waveform debug(Verdi) and formal tools like Jasper.
• Exposure to Test Bench Accelerators /Emulation Platforms.