662 Systemverilog Jobs - Page 4

Bangalore,Karnataka,India Job ID 771286 About Us: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What we offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced design technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. Key Responsibilities: Develop ASIC IP blocks and subsystems, contributing to the advancement of 5G and 6G communication technology. Take full ownership of a design, whether at the block or subsystem level. Generate comprehensive documentation throughout the design lifecycle. Perform digital design and conduct all RTL sign-off checks. Continuously enhance and optimize design methodologies and processes. Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications. Work closely with verification engineers to review and refine verification plans. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 10+ years industry experience in ASIC IP Design. Strong Experience in/with: Understanding of ASIC technology, design environments, and methodologies. SystemVerilog RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. AMBA-based designs such as AXI and CHI. SystemVerilog Assertions. Additional Requirements Experience with Cadence and Synopsys front-end and middle-end design suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Expertise in low-power design, including specifying power intent using UPF or similar standards. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: ARM-based embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

Bangalore,Karnataka,India Job ID 771287 About Us: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What we Offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. If you are passionate about ASIC IP verification engineering and eager to contribute to cutting-edge projects in a global setting, we encourage you to apply. Key Responsibilities: Take part of the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 10+ years industry experience in ASIC IP verification using SystemVerilog and UVM. Strong experience in / with: Development of verification test plans and create directed/randomized test cases. Formal verification. In implementing scoreboards, checkers, bus functional models in existing testbench environment. AMBA-based designs such as AXI and CHI. SystemVerilog Assertions. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: ARM-based real-time embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in using ASIC development tools such as Lint, CDC, Design compiler, and Primetime is necessary. An understanding of constraint development and timing closure will be a plus. Experience in Synthesis and knowledge of timing concepts will also be beneficial. Additionally, experience in creating padring and collaborating with the chip-level floorplan team is desirable. You must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of relevant experience or a PhD with 4+ years of relevant experience will also be considered. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities in the hiring process. The company expects all employees to adhere to relevant policies and procedures, including security protocols and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to submit profiles, applications, or resumes through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers.,

About QpiAI: QpiAI is at the forefront of discovering optimal AI and Quantum systems across various industries including Life sciences, Healthcare, Transportation, Finance, Industrial, and Space technologies. Specializing in building full stack Enterprise Quantum Computers, the Quantum hardware team at QpiAI is dedicated to the design and characterization of Quantum Processor, Cryogenic Quantum Control Circuits, RF Control Hardware, and QpiAI ASGP. We are looking for a talented Hardware Design Engineer to join our innovative team. Together, we aim to develop cutting-edge custom hardware for Quantum computers that have the potential to revolutionize various sectors. If you are a self-driven individual with a solid grasp of building complex SOC and IPs, possess a deep understanding of client requirements, and are familiar with different development cycles, then this opportunity is tailored for you. Responsibilities: - Engage in micro-architecture development and document specifications. - Implement designs in RTL and collaborate with the verification team to ensure functionality. - Utilize logic design expertise to optimize performance and power objectives. - Produce a synthesis/timing clean design while cooperating with the physical design team for a routable and physically implementable design. Requirements: - Bachelor's degree in electrical engineering or computer engineering. - 3+ years of experience in chip design development for complex designs. - Proficiency in logic design, Verilog, and/or System-Verilog, with a strong understanding of physical design and VLSI. - Excellent interpersonal skills and a team player mindset. - Familiarity with design reuse, including RTL, constraints, and waiver. - Experience in handling timing constraints and exceptions. - Ability to conduct standard quality checks such as LINT and CDC. Join us at QpiAI and be part of a dynamic team driving advancements in Quantum computing hardware to shape the future of technology across multiple industries.,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dedicated and detail-oriented Formal Verification Engineer with a passion for ensuring the reliability and functionality of complex design IPs. You excel in a collaborative environment, working closely with designers, architects, and verification engineers to drive verification projects to success. You possess a solid understanding of hardware micro-architecture and design, and you are proficient in HDLs like Verilog and SystemVerilog. Your problem-solving skills are top-notch, and you are familiar with formal property verification concepts and tools. You are eager to contribute to a team that is at the forefront of technological innovation and excellence. What You’ll Be Doing: Helping decide on the best applications of formal verification techniques to various parts of the design. Reviewing functional and micro-architectural specifications to define the scope for formal verification. Creating high-quality formal verification test plans to sign off on the corresponding design implementation. Building formal verification testbenches, coding assertions and constraints, and applying abstraction techniques. Applying formal coverage techniques to analyze over-constraints and measure functional coverage. Collaborating closely with the Synopsys Tool Development Group to drive verification projects. The Impact You Will Have: Ensuring the reliability and functionality of complex design IPs through rigorous formal verification. Contributing to the development of high-quality IP that meets the stringent requirements of our clients. Driving innovation in verification methodologies and techniques. Collaborating with a talented team to achieve project milestones and goals. Enhancing the overall quality and performance of Synopsys' product offerings. Playing a key role in the success of various high-profile projects within the company. What You’ll Need: Pursuing or completed BTech/MTech degree in Electrical Engineering, Computer Engineering, or a related field. Good understanding of hardware micro-architecture and design. Proficiency in HDLs like Verilog and SystemVerilog. Familiarity with SystemVerilog Assertions (SVA) and basic concepts of formal property verification. Good debugging and problem-solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal and communication skills and a dream to work as a great team member. Who You Are: An excellent communicator who can articulate complex ideas clearly and effectively. A team player who thrives in a collaborative environment. A detail-oriented individual with strong analytical and problem-solving skills. A proactive learner who stays updated with the latest industry trends. A highly motivated and driven professional with a passion for technology. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on formal verification engineering. Our team is dedicated to ensuring the reliability and functionality of complex design IPs through rigorous verification methodologies. We value collaboration, creativity, and excellence, and we are committed to pushing the boundaries of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

As a Sr. Engineer in ASIC Verification at Synopsys, you will play a crucial role in ensuring the robustness and reliability of our digital designs through meticulous verification processes. Your expertise in high-speed protocols and strong foundation in Verilog, VHDL, and/or SystemVerilog will empower you to identify verification environment requirements and develop complex UVM verification environments. Your proactive approach to problem-solving and excellent communication skills will enable you to collaborate effectively with cross-functional teams and contribute to the success of our cutting-edge projects. Your responsibilities will include generating verification test plans, defining and verifying complex UVM verification environments, evaluating various aspects of the development flow, and identifying design problems to propose corrective actions. By enhancing the overall quality and performance of our silicon IP products, you will help drive continuous improvements in our verification methodologies and practices. Your passion for learning and exploring new technologies, coupled with your 3+ years of relevant experience in ASIC digital verification, will be instrumental in supporting the growth and success of both our projects and Synopsys as a whole. You will be part of an experienced and dedicated digital design and verification team at Synopsys, where excellence and continuous improvement are key priorities. Working in a dynamic and fast-paced environment, you will have the opportunity to collaborate with experts in various fields, learn from their insights, and contribute significantly to the success of our innovative projects. If you are a detail-oriented, innovative engineer with a proven desire to explore new technologies and a proactive approach to addressing challenges, we invite you to join us in shaping the future through continuous technological innovation. In return for your contributions, we offer a comprehensive range of health, wellness, and financial benefits tailored to meet your needs. Your recruiter will provide detailed information about the salary range and benefits during the hiring process. If you are ready to make a meaningful impact in the Era of Smart Everything, we look forward to welcoming you to our team at Synopsys.,

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence IP Tensilica group is a leading provider of configurable embedded processor technology, with a growing presence in the Automotive Safety market. As a member of the Functional Safety Design Verification Team for Xtensa processors you will be responsible for development and verification of hardware and software safety mechanisms. You will implement simulation or emulation test benches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target safety and product verification goals. You will also assist with fault simulation and analyzing coverage information. You will work closely with the RTL, EDA, and Functional Safety teams. You will develop and deliver functional safety work products, including documentation needed for product safety certification. Required Skills And Experience 8-10 years of design verification experience BS (or higher) in EE/Computer Engineering Experience in leading a small team Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage Good working knowledge of scripting languages like Perl, Unix shell or similar languages Knowledge of technical safety concepts and requirement specifications according to ISO 26262 Proficient with C language and assembly language Excellent written and oral communication skills necessary Exposure to debugging netlist/gate level simulation. General understanding OS. Exposure to MISRA coding guidelines Experience in fault simulation tools and methodologies Were doing work that matters. Help us solve what others cant. Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: THE ROLE: This role will be part of Silicon Applications and Documentation engineering team in AECG. You will be working with a collaborative team focused on enabling customers to succeed when using ACAP/FPGA. You will have the opportunity to focus on Complex IPs and memory interfaces on the ACAP/FPGA platforms for specialty applications such as image sensors, IOT, emulation etc... In this cross-functional position you will interface directly with Design and Software engineering groups, and you will be the primary interface between the engineering teams and escalated customer support issues. THE PERSON: You are a team player who has excellent communication and writing skills. You have experience communicating effectively and working optimally with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are interested in debugging customer issues and leading complex projects. KEY RESPONSIBILITIES: As a member of this team, you will be responsible for the following: Creating customer documentation (datasheets, architecture manuals, product guides, errata, tutorials) Validating and characterizing memory/IO interfaces and other FPGA key features Building custom designs using Verilog, SystemVerilog or VHDL Resolving escalated customer support issues PREFERRED EXPERIENCE: Excellent written and verbal communication skills. Effective project planning and execution FPGA or ASIC design background Strong background in memory interfaces Experience in Silicon Bring-up and Hardware debug Strong background in RTL development and verification Familiarity with programming/scripting language ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

#Connections #Hiring #VerificationEngineer #Hyderabad #Experience Hi Connections, We are hiring.... Job Title: Verification Engineer Location: Hyderabad / Bangalore / Hybrid Department: Semiconductor / VLSI Design Verification Employment Type: Full-Time Experience: 3+Years Job Summary We are seeking a detail-oriented Verification Engineer to ensure functional correctness and robustness of complex SoC/ASIC designs. The role involves creating verification environments, developing testbenches, executing test plans, and debugging issues in collaboration with RTL, architecture, and physical design teams. Key Responsibilities ● Develop and execute verification plans based on architecture and design specifications. ● Create SystemVerilog/UVM-based testbenches for block-level and top-level verification. ● Implement constrained-random, directed, and coverage-driven verification methodologies. ● Perform functional coverage analysis to ensure thorough testing. ● Debug RTL issues by analyzing simulation waveforms and working with design engineers. ● Integrate third-party IPs and verify their functionality in the system. ● Automate regression runs and maintain test environments. ● Document verification processes, results, and closure reports. Required Skills & Qualifications ● Bachelor’s/Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or related field. ● 3+ years of experience in ASIC/SoC verification. ● Strong proficiency in SystemVerilog and UVM methodology. ● Experience with simulation tools (Synopsys VCS, Cadence Xcelium, Mentor QuestaSim). ● Understanding of AMBA protocols (AXI, AHB, APB) and other standard interfaces. ● Familiarity with functional coverage, code coverage, and assertion-based verification (SVA). ● Strong debugging skills using waveforms and simulation logs. Preferred Qualifications ● Experience with low-power verification (UPF/CPF). ● Knowledge of FPGA-based verification and emulation platforms. ● Exposure to AI/ML accelerator verification or DSP systems. ● Familiarity with Python/TCL/Perl scripting for automation. ● Experience with formal verification tools (JasperGold, VC Formal). Interested guys, kindly share your updated profile to pavani@sandvcapitals.com or reach us on 7995292089. Thank you. Job Type: Full-time Pay: ₹1,200,000.00 - ₹1,500,000.00 per year Experience: ASIC/SoC Verification: 3 years (Required) Work Location: In person

You will need a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. It is essential to have experience in verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or C/C++. Additionally, you should have experience with verification components and environments in standard verification methodology, as well as experience in verifying digital systems using standard Internet Protocols (IP) components/interconnects. Familiarity with coding languages and software development frameworks is also required. A Master's degree in Electrical Engineering or Computer Science, or a PhD in Electrical Engineering or Computer Science, or equivalent practical experience is preferred. Candidates with an architectural background in Hierarchies, Coherency, Memory Consistency Models, Peripheral Component Interconnect Express (PCIe), Packet Processors, Security, or Clock and Power Controllers will be given preference. Experience with building verification methodologies that span simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is also desirable. Additionally, experience with performance verification of System on a Chip (SOCs), pre-Silicon analysis, and post-Silicon correlation, as well as familiarity with Interconnect Protocols, is a plus. As part of the team developing custom silicon solutions for Google's direct-to-consumer products, you will have the opportunity to contribute to innovative products with a global reach. Your role will involve shaping the next generation of hardware experiences, focusing on delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. By combining the best of Google AI, Software, and Hardware, our team strives to create profoundly helpful experiences through research, design, and development of new technologies and hardware. Your responsibilities will include planning and executing the verification of the next generation configurable Infrastructure Internet Protocols (IPs), interconnects, and memory subsystems. You will be expected to create and enhance constrained-random verification environments using SystemVerilog, develop cross-language tools and scalable verification methodologies, identify and write various coverage measures for stimulus and corner-cases, and collaborate with design engineers to debug tests and deliver functionally correct blocks and subsystems. Closing coverage measures to identify verification gaps and demonstrate progress towards tape-out will also be part of your role.,

To apply to a Varex Imaging position, please create an account and sign-in. CURRENT VAREX IMAGING EMPLOYEES: Please apply by logging into your internal Workday Account. Analyzes, designs, programs, debugs and modifies FPGA code designs. Troubleshoots code for firmware (IC embedded code) applications. Work often involves analog and digital hardware and software operating systems. Position requires knowledge and exposure to hardware design. Typically, programs in - Hardware Description Languages (e.g., SystemVerilog or VHDL) or high-level languages (e.g., Python). FPGA / Embedded Firmware Engineer (Firmware Engineer III) Varex Imaging is seeking a FPGA / Embedded Firmware Engineer in the fast-growing X-Ray Imaging Components division. This individual will work in our India facility. The developer will bring value to the team by developing firmware systems and libraries needed to process and manage flat panel x-ray detectors data used in medical and industrial imaging systems. Candidates are expected to thrive in a fast-paced, self-directed environment and work both individually and with a team of highly skilled FPGA engineers. Responsibilities include writing HDL code, developing/implementing efficient algorithms interacting with x-ray hardware components, and developing low-level component interfaces in both FPGA and embedded software. Your Role: - Experience with Verilog, SystemVerilog, and/or VHDL - Knowledge of FPGA development basics - Familiarity with simulation tools like Modelsim or equivalent - Proficiency in a scripting language such as Python - Some experience with debugging electrical hardware using Chipscope/Signaltap or oscilloscope/logic analyzer Your Profile: - B.S. in Electrical Engineering, Physics, Computer Science, or related field with 5+ years of relevant experience, or M.S. or Ph.D. with 2+ years of relevant experience - Experience with Windows & Linux - Familiarity with Object-oriented Design and Analysis (OOA and OOD) is a plus - Ability to develop specifications & requirements - Design, build, and unit test firmware in a collaborative environment - Knowledge/use of automated test benching is beneficial - Familiarity with the use of FPGA intellectual property is advantageous - Excellent oral and written communication skills - Must be able to work with minimal supervision - Proficient in utilizing business tools such as E-mail, Microsoft Word, Excel, and PowerPoint What we offer: - A unique opportunity to become part of a growing organization in India within a global market leader in X-ray imaging components - Excellent development potential - An international work environment with global teams collaborating on various projects across multiple countries - Competitive compensation package including participation in Varex incentive plans - Corporate Health Benefits - Additional benefits will be added as we grow Time Type: Full time Job Type: Regular Work Shift: N/A Salary: Not specified,

We are seeking a Director of Engineering (Design Verification) to oversee and expand our DV practice. With over 15 years of experience in SoC/ASIC verification, exceptional technical expertise, demonstrated leadership abilities, and the talent to motivate high-performing teams, you will play a pivotal role in our organization. Responsibilities include leading end-to-end SoC/ASIC Design Verification programs, establishing DV methodologies, flows, and best practices (UVM, SV, C-based), delivering technical leadership and practical problem-solving, managing and guiding top-performing engineering teams, collaborating with cross-functional teams for project success, driving customer engagement, ensuring delivery excellence, and supporting business development through pre-sales and technical discussions. The ideal candidate will possess a minimum of 15 years of semiconductor design verification experience, including at least 5 years in a leadership capacity. Proficiency in SystemVerilog, UVM, C/C++ co-simulation, and testbench architecture is essential. In-depth knowledge of ARM architecture, AMBA protocols (AXI, CHI, APB), high-speed interfaces (PCIe, DDR, Ethernet), Formal Verification, GLS, coverage closure, GLS methodology/flows, VIP Integration & Sequence usage, C-SV co-simulation, and Python scripting is required. Strong skills in people management, mentoring, and stakeholder engagement are also critical. Joining Seminovaa offers you the chance to be part of a rapidly growing semiconductor services company, led by its founder. You will have the opportunity to shape and lead the Design Verification practice, working on cutting-edge projects in AI, Automotive, Networking, and High-Performance Computing. Our collaborative, innovation-driven culture provides global exposure and a dynamic work environment. Apply now by sending your profile to careers@seminovaa.com. #SemiconductorJobs #VLSICareers #ChipDesign #NowHiring #Seminovaa #DFTengineers #Verificationengineers #PhysicalDesignEngineers,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role This role will be part of Silicon Applications and Documentation engineering team in AECG. You will be working with a collaborative team focused on enabling customers to succeed when using ACAP/FPGA. You will have the opportunity to focus on Complex IPs and memory interfaces on the ACAP/FPGA platforms for specialty applications such as image sensors, IOT, emulation etc... In this cross-functional position you will interface directly with Design and Software engineering groups, and you will be the primary interface between the engineering teams and escalated customer support issues. The Person You are a team player who has excellent communication and writing skills. You have experience communicating effectively and working optimally with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are interested in debugging customer issues and leading complex projects. Key Responsibilities As a member of this team, you will be responsible for the following: Creating customer documentation (datasheets, architecture manuals, product guides, errata, tutorials) Validating and characterizing memory/IO interfaces and other FPGA key features Building custom designs using Verilog, SystemVerilog or VHDL Resolving escalated customer support issues Preferred Experience Excellent written and verbal communication skills. Effective project planning and execution FPGA or ASIC design background Strong background in memory interfaces Experience in Silicon Bring-up and Hardware debug Strong background in RTL development and verification Familiarity with programming/scripting language Academic Credentials Bachelors or Masters degree in Computer Engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job description Meta is looking for Design Verification Engineering Manager to join our dynamic team and embark on a rewarding career journey. Lead verification strategies for complex chip designs. Oversee testbench development and execution. Ensure compliance with verification methodologies.

Job description Meta is looking for ASIC Engineer, Accelerator Systems to join our dynamic team and embark on a rewarding career journey. Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills

Job description Meta is looking for ASIC Engineer, Design Verification to join our dynamic team and embark on a rewarding career journey. Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills

Job description ASIC Engineer, Architecture Responsibilities Work on advanced architecture, algorithms and models targeting Machine Learning solutions. Analyze and map data center workloads to ASIC architecture, as well as develop performance and functional models to validate the architecture. Implement and analyze algorithms and enhanced architecture for the data center Machine Learning accelerators. Implement various models needed for the validation of the accelerators. Create Machine Learning kernels to analyze the ASIC Architecture, and make the architecture optimal for ML workloads. Minimum Qualifications Currently has, or is in the process of obtaining, a Bachelors degree in Electrical Engineering, Computer Engineering or related field More than 2 years of industry experience and knowledge of Computer Architecture concepts such as processor architecture, memory systems and on-chip interconnection networks. Programming skills in C, C++ or related Object Oriented Programming Preferred Qualifications Master s or PhD degree in Electrical Engineering, Computer Engineering or related areas. Experience in modeling, and driving power and performance trade-offs in ASIC Architecture. Experience and knowledge in Machine Learning Silicon architectures.

Job description ASIC Engineer, Architecture Responsibilities Work on advanced architecture, algorithms and models targeting Machine Learning solutions. Analyze and map data center workloads to ASIC architecture, as well as develop performance and functional models to validate the architecture. Implement and analyze algorithms and enhanced architecture for the data center Machine Learning accelerators. Implement various models needed for the validation of the accelerators. Create Machine Learning kernels to analyze the ASIC Architecture, and make the architecture optimal for ML workloads. Minimum Qualifications Currently has, or is in the process of obtaining, a Bachelors degree in Electrical Engineering, Computer Engineering or related field More than 2 years of industry experience and knowledge of Computer Architecture concepts such as processor architecture, memory systems and on-chip interconnection networks. Programming skills in C, C++ or related Object Oriented Programming Preferred Qualifications Master s or PhD degree in Electrical Engineering, Computer Engineering or related areas. Experience in modeling, and driving power and performance trade-offs in ASIC Architecture. Experience and knowledge in Machine Learning Silicon architectures.

Job description Meta is looking for ASIC Engineer, SoC Architect to join our dynamic team and embark on a rewarding career journey. Your role involves working on complex projects and ensuring that ASICs meet performance, power, and area requirements. Key Responsibilities : Design Planning : Collaborate with cross-functional teams to define project goals, scope, and design requirements for ASIC projects. Establish design plans, including specifications, milestones, and budgets. Architecture and Microarchitecture : Create architectural and microarchitectural specifications for ASIC designs, outlining high-level structure and functionality . RTL Design : Implement ASIC designs using hardware description languages (HDL) such as Verilog or VHDL. Develop and optimize RTL (Register Transfer Level) code for logic design. Synthesis and Optimization : Perform synthesis and optimization to ensure the ASIC design meets performance, power, and area targets. Work on clock domain crossing, power management, and timing closure. Verification Support : Collaborate with ASIC Verification Engineers to develop and implement testbenches and test scenarios to validate ASIC functionality. Debug and resolve design issues identified during verification. DFT (Design for Test) : Implement DFT features, such as scan chains and boundary scan, to facilitate efficient testing of the ASIC. Low- Power Design : Optimize ASIC designs for low-power operation, including clock gating, voltage scaling, and power gating. Physical Design Support : Work with physical design and layout teams to ensure proper floor planning and placement of ASIC components. Documentation : Maintain comprehensive and well-organized documentation of design specifications, RTL code, and design decisions. Technology and Tool Awareness : Stay updated on semiconductor technologies, ASIC design tools, and industry best practices to enhance design processes .Collaboration : Collaborate closely with cross-functional teams, including verification, software, and project management, to achieve project goals.

Job description Meta is looking for ASIC Engineer, SoC Architect (AI Accelerators) to join our dynamic team and embark on a rewarding career journey. Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills

Job description Meta is looking for ASIC Engineer, Architecture to join our dynamic team and embark on a rewarding career journey. Your role involves working on complex projects and ensuring that ASICs meet performance, power, and area requirements. Key Responsibilities : Design Planning : Collaborate with cross-functional teams to define project goals, scope, and design requirements for ASIC projects. Establish design plans, including specifications, milestones, and budgets. Architecture and Microarchitecture : Create architectural and microarchitectural specifications for ASIC designs, outlining high-level structure and functionality. RTL Design : Implement ASIC designs using hardware description languages (HDL) such as Verilog or VHDL. Develop and optimize RTL (Register Transfer Level) code for logic design. Synthesis and Optimization : Perform synthesis and optimization to ensure the ASIC design meets performance, power, and area targets. Work on clock domain crossing, power management, and timing closure. Verification Support : Collaborate with ASIC Verification Engineers to develop and implement testbenches and test scenarios to validate ASIC functionality. Debug and resolve design issues identified during verification. DFT (Design for Test) : Implement DFT features, such as scan chains and boundary scan, to facilitate efficient testing of the ASIC. Low-Power Design : Optimize ASIC designs for low-power operation, including clock gating, voltage scaling, and power gating. Physical Design Support : Work with physical design and layout teams to ensure proper floor planning and placement of ASIC components. Documentation : Maintain comprehensive and well-organized documentation of design specifications, RTL code, and design decisions. Technology and Tool Awareness : Stay updated on semiconductor technologies, ASIC design tools, and industry best practices to enhance design processes. Collaboration : Collaborate closely with cross-functional teams, including verification, software, and project management, to achieve project goals.

Job description Meta is looking for ASIC Engineer, Design Verification to join our dynamic team and embark on a rewarding career journey. Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills

As an experienced FPGA Design Engineer in the field of wireless communication, you will be joining the core R&D team of our client, a leading company specializing in optical wireless communication (OWC) and LiFi technology. Your primary responsibility will be to work on high-speed wireless communication systems, starting from the conceptualization phase all the way to integration. Your key responsibilities will include FPGA design and development utilizing VHDL, Verilog, or SystemVerilog. You will focus on implementing high-speed digital designs with an emphasis on modulation/demodulation techniques such as QPSK, QAM, and OFDM. Additionally, you will lead technical project teams to ensure timely delivery within budget constraints. Developing communication system architectures for wireless networks and staying abreast of FPGA advancements and multi-core microprocessor platforms will also be part of your role. To excel in this position, you are required to hold a Master's or PhD in FPGA/RTL Design or a related field, along with a minimum of 5 years of experience in FPGA design, particularly in wireless communication domains like 3G, 4G, WiFi, and WiMax. Strong verification skills for high-speed design implementation, a solid understanding of networking protocols, and wireless communication concepts are essential. Your analytical, problem-solving, and teamwork skills will also be critical to your success in this role. This opportunity offers you the chance to work on cutting-edge LiFi technology with global deployment potential. You will be part of an innovative and fast-growing R&D environment that provides opportunities for rapid career advancement based on your performance.,

Company Description At QualSoC, we empower innovation through cutting-edge semiconductor solutions. Driven by our tagline, "Creative Minds & Innovative Solutions", we are committed to providing businesses with the expertise and resources they need to thrive in todays competitive landscape. Our dedicated team of professionals ensures seamless integration of our services into operations, enabling enhanced productivity and efficiency. Role Description This is a full-time on-site role for a Design Verification Engineer at our location in Karaikal. The Design Verification Engineer will be responsible for developing and implementing verification environments and methodologies, writing test plans, and executing test cases. Daily tasks include debugging, trouble-shooting, and working closely with design and system engineers to ensure the highest quality of the delivered silicon. The role also involves participation in verification reviews and continuous improvement of verification processes and methodologies. Qualifications Experience with Verification methodologies such as UVM, SystemVerilog, and functional coverage Skills in Testbench development and simulation Strong debugging and troubleshooting skills Proficiency in hardware description languages like VHDL/Verilog Strong understanding of digital design fundamentals Experience in scripting languages (Python, Perl, etc.) Excellent analytical and problem-solving skills Bachelors degree in Electrical Engineering, Computer Engineering, or related field Experience in the semiconductor industry is a plus Good communication and teamwork skills Show more Show less

As a highly skilled R&D Staff Engineer at Synopsys, you will be at the forefront of designing and developing state-of-the-art EDA tools with innovative algorithms for static low power verification products. With your expertise in C/C++, data structures, and algorithms, you will collaborate with local and remote teams to ensure seamless integration and execution. Your background in Electronic Design Automation (EDA) tools and methodologies, along with your proficiency in Verilog, SystemVerilog, and VHDL, will position you as a leader in the field. Your responsibilities will include working directly with customers to understand their requirements, providing online debugging, and tracking delivery and execution. You will lead a small team, guiding them through technical challenges and project milestones, while contributing to the continuous improvement of the static low power verification product. Additionally, you will explore new architectures and lead the development of cutting-edge solutions. Your impact will be significant as you drive the development of advanced EDA tools, enhance the quality and reliability of the static low power verification product, and provide critical support to customers. By leading and mentoring junior engineers, you will foster a culture of innovation and excellence within the team, contributing to Synopsys" reputation as a leader in the semiconductor and EDA industries. Your role will be pivotal in the successful execution of projects, meeting deadlines, and exceeding expectations. To excel in this role, you will need fluency in C/C++, a strong background in data structures and algorithms, experience with UPF, familiarity with Tcl and Python-based development on Unix, and knowledge of Verilog, SystemVerilog, and VHDL HDL. Your ability to develop new architectures and demonstrate strong leadership skills will be crucial to your success. As a dynamic and innovative engineer with a passion for technology and a commitment to quality, you will play a key role in a collaborative and productive work environment. Your problem-solving skills, critical thinking ability, and self-motivation will be assets that drive your success in this role. By being detail-oriented and setting high standards for quality and reliability, you will make valuable contributions to the team. You will be part of the Static Verification team at Synopsys, working alongside talented engineers dedicated to developing and enhancing static low power verification products. This team collaborates closely with other departments to ensure seamless integration and execution, contributing to the success of Synopsys and its customers. Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process. Join us at Synopsys to transform the future through continuous technological innovation.,