662 Systemverilog Jobs - Page 6

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 8+/6+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills. Who You'll Work With Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world! We Are Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!

5 - 7 Years 1 Opening Noida Role description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes: Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures of Outcomes: Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected: Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely delivery: Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills development: Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work: Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity: Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples: Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples: Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments: Responsibility- Primary responsibility includes I/O, Macro Characterization, EDA View generation (Functional, Electrical and Physical) & Full package validation. He/she needs to be in constant contact with IP design experts to understand the IP design (schematic, Layout) & IP specification (more electrical characteristics and functional aspect). Must have skills: • Excellent understanding of digital design concepts and CMOS fundamentals. • Ability to quickly comprehend the functional and electrical specifications of custom/full custom IPs. • Proficient in IO/Standard cells/Memory characterization flow using industry-standard tools such as Kronos, Liberate, and Silicon Smart. • Strong understanding of various formats of liberty files, including NLDM, CCS, and LVF. • Skilled in custom layout and schematic design/updates. • Experienced in IP physical model generation (LEF, sign-off GDS, CDL) and conducting validation checks (DRC, LVS, ERC) with debugging skills. • Proficient in behavioral modeling using Verilog/SystemVerilog and testbench writing. • Experience in IBIS (Input/Output Buffer Information Specification) modeling is a plus. • Excellent team player who is disciplined, adaptable, and possesses strong communication skills. Qualification & Experience • B. Tech / M. Tech – Electronics/VLSI Engineering • 3 to 7 years of professional experience in EDA/CAD View generation domain. • Prior ST experience even as intern is preferred. Skills CAD Design engineer,Standard Cell,Cmos About UST UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

NVIDIA is at the forefront of innovation, constantly evolving and adapting to new opportunities that have a global impact. As a DFT Verification Engineer at NVIDIA, you will be part of a team that works on groundbreaking innovations in Design-for-Test (DFT) Engineering, focusing on crafting creative solutions for DFT architecture, implementation, verification, and post-silicon validation on some of the industry's most complex semiconductor chips. Your role will involve implementing the best verification methodologies for DFT IP at unit and system levels, utilizing your expertise in SystemVerilog, UVM, FPGA, and Emulation applications in the DFT domain. You will have the opportunity to build state-of-the-art verification test benches and methodologies, develop verification environments using UVM, and create reusable bus functional models, monitors, checkers, and scoreboards to achieve functional coverage-driven verification closure. Collaboration with cross-functional teams such as chip architecture, ASIC design, functional verification, and post-silicon teams will be a key aspect of your responsibilities. You will work towards improving the quality of DFT methods and strive for innovation in this realm. To qualify for this role, you should hold a BSEE with 3+ years or MSEE with 2+ years of experience in IP verification or related domains. Expertise in System Verilog, UVM/VMM verification methodologies, prototyping tools, and ASIC design methodologies is essential. Strong programming/scripting skills in C++, Perl, Python, or Tcl, along with excellent communication skills, analytical thinking, and problem-solving abilities are also required. If you have a strong background in both DFT and RTL Verification domains, knowledge of formal verification methodologies and tools, and hands-on experience in post-silicon debug, you will stand out from the crowd. Join NVIDIA in amplifying human imagination and intelligence by making the choice to be part of our team today. NVIDIA is an equal opportunity employer.,

As a Lead Product Validation Engineer at Cadence in Noida, you will have the opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and make a significant impact. Cadence, a pivotal leader in electronic design, leverages over 30 years of computational software expertise to deliver software, hardware, and IP that bring design concepts to life. Our customers are the world's most innovative companies, driving exceptional electronic products across various market applications. At Cadence, we prioritize our employees" well-being by offering employee-friendly policies that focus on physical and mental health, career development, learning opportunities, and celebrating success tailored to individual needs. Our unique One Cadence - One Team culture fosters collaboration within and across teams to ensure customer success. You will be part of a diverse team of passionate and talented individuals dedicated to exceeding expectations for customers, communities, and each other every day. Your responsibilities as a Lead Product Validation Engineer include being an Electrical, Electronics, or Computer Science Engineer with a solid understanding of HDLs like Verilog and/or VHDL. You should have experience in simulation/emulation using these languages and a good working knowledge of EDA tools (Cadence/Other) to debug design/verification issues. The role requires experience in process automation with scripting, familiarity with SystemVerilog, C++, UVM, and Functional Verification of complex digital systems like SoC Verification using SystemVerilog. Additionally, knowledge of protocols such as PCIe, USB3/4, and DP is advantageous. The ideal candidate should hold a B. Tech or M. Tech/B.E./M.E. with 3-6 years of relevant experience. Strong written, verbal, and presentation skills are essential, along with the ability to establish close working relationships with customers and management. You should have a knack for exploring unconventional solutions to get the job done and work effectively across functions and geographies while maintaining integrity. Join Cadence in solving challenges that others can't, and be a part of work that truly matters.,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is seeking highly motivated and talented professionals to join their R&D center in Bengaluru. Eridu AI is a Silicon Valley-based hardware startup specializing in infrastructure solutions that enhance the performance of large-scale AI models. The company has introduced innovative advancements in semiconductors, software, and systems to address system-level bottlenecks, maximize GPU utilization, reduce costs, and enhance data center efficiency, which have been recognized by leading hyperscalers. Led by a team of experienced Silicon Valley executives and engineers, including serial entrepreneur Drew Perkins, Eridu AI is at the forefront of developing cutting-edge technologies. They are currently looking for experienced RTL designers to contribute to defining and implementing their industry-leading Networking ASICs. If you are a self-driven individual passionate about solving real-world problems, this is a unique opportunity to influence the future of AI Networking. As part of the Design Group, you will play a key role in defining, specifying, architecting, executing, and productizing state-of-the-art Networking chips. Your responsibilities will include working on microarchitecture, design implementation, testing, performance optimization, protocol support, troubleshooting, and debugging related to high-speed networking ASICs. Additionally, you will collaborate with cross-functional teams to ensure the functionality and reliability of the designs. To be considered for this role, you should have a ME/BE degree with a minimum of 8-15 years of experience, hands-on knowledge of SystemVerilog and Verilog, a solid understanding of ASIC design methodologies, expertise in designing and optimizing scheduling and QoS mechanisms, familiarity with Ethernet and IP protocols, strong analytical and problem-solving skills, and excellent communication abilities. Joining Eridu AI will offer you the chance to work with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary will be determined based on various factors, including skills, experience, qualifications, and market trends. For more information about the company, please visit eridu.ai.,

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. Experience designing and implementing complex functional verification environments is required. Knowledge of protocols like PCIe, USB3/4, DP an added advantage. Were doing work that matters. Help us solve what others cant. Show more Show less

As an experienced HDL design/verification engineer at Lattice Semiconductors, you will play a pivotal role in designing, developing, and enhancing simulation capabilities within Lattice Radiant, the official FPGA design tool. Working closely with hardware developers and QA teams, you will be responsible for enabling and supporting simulation workflows for Verilog, VHDL, and SystemVerilog across various Lattice FPGA families. Your key responsibilities will include diagnosing and resolving simulation issues, validating and testing simulation features, contributing to automation scripts and testbench generation tools, as well as maintaining simulation documentation, troubleshooting guides, and user tutorials. You will have the opportunity to work on cutting-edge technologies and have a direct impact on the evolution of FPGA development tools and methodology. To excel in this role, you must possess a Bachelor's or Master's degree in Electronics Engineering or a related field, along with solid experience in hardware description languages (HDLs) and simulation tools such as Modelsim and Synopsis VCS. A strong understanding of HDL simulation concepts, EDA tool development, FPGA architectures, and configuration flows is essential. Industrial experience in a similar field for more than 5 years is a requirement. Preferred skills for this role include strong analysis and debugging capabilities, as well as excellent communication and cross-disciplinary collaboration skills. In return, Lattice Semiconductors offers competitive compensation, comprehensive benefits, a highly collaborative and intellectually driven team environment, and supportive cross-geo team environment with technical mentorship. If you thrive in a fast-paced, results-oriented environment and are looking to contribute to a dynamic team, Lattice Semiconductors may be the perfect fit for you.,

Job Titles: Senior Staff ASIC Verification Engineer- Pune Location We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and passionate ASIC Digital Verification engineer, ready to take on technical leadership in a dynamic, high-impact environment. With a proven track record of developing and validating complex UVM verification environments, you thrive in collaborative settings and enjoy mentoring others. You bring a deep understanding of digital verification flows, simulation, and coverage analysis, and you excel at identifying and solving challenging design problems. Your experience spans 8-15+ years in ASIC verification, where you've consistently demonstrated your ability to architect, plan, and execute verification strategies. You’re comfortable multitasking between multiple projects and have a genuine desire to stay at the forefront of emerging technologies. You communicate effectively in both written and spoken English, and your organizational skills help ensure that projects are delivered on time and to the highest quality standards. You’re motivated by the opportunity to make a significant impact, not just through your own work, but by elevating the entire team around you. Your proactive approach to learning, problem-solving, and process improvement defines your professional ethos. What You’ll Be Doing: Identify verification environment requirements from specifications, design functionalities, and interfaces. Generate comprehensive verification test plans and maintain detailed documentation for verification environments and their usage. Define, develop, and verify advanced UVM (Universal Verification Methodology) environments for complex ASIC designs. Evaluate and exercise all aspects of the verification flow, including Verilog/SystemVerilog development, functional simulation, constraint development, behavioral modeling, and coverage metrics analysis (functional and code coverage). Collaborate closely with architects, designers, and the VIP team to ensure seamless integration and accomplishment of project goals. Identify design problems, propose corrective actions, and resolve inconsistencies in documented functionalities. Mentor and guide junior engineers, supporting them in debugging and solving complex verification problems. Support customer issues through issue reproduction and in-depth analysis, ensuring customer satisfaction. Drive continuous improvement of verification methodologies and execution efficiency within the team. Adhere to best practices, quality standards, and maintain a high level of test and verification rigor. The Impact You Will Have: Accelerate the delivery of robust, high-quality ASIC products by ensuring thorough and systematic verification. Enhance the team’s technical capabilities by sharing expertise and mentoring junior engineers. Directly contribute to Synopsys’ reputation for excellence in silicon design and verification solutions. Drive innovation in verification methodologies, raising the bar for future projects and industry standards. Improve customer satisfaction by providing expert support and resolving technical challenges efficiently. Facilitate cross-functional collaboration, fostering a culture of knowledge sharing and continuous learning. What You’ll Need: 8-15+ years of hands-on experience in ASIC digital verification, preferably in a lead or staff engineering capacity. Proficiency in Verilog, VHDL, and/or SystemVerilog languages, with a strong grasp of modern verification methodologies such as UVM. Experience in developing and debugging verification environments, including test planning, simulation, and coverage analysis. Familiarity with industry-standard scripting languages (BASH, TCSH, PERL, PYTHON, TCL) for automation and workflow optimization. Excellent written and spoken English communication skills, with the ability to document and present technical concepts clearly. Strong organizational skills, with experience managing multiple priorities and delivering high-quality results under tight deadlines. Who You Are: Innovative and proactive, with a passion for continuous learning and embracing new technologies. Collaborative team player who thrives in a diverse, multicultural environment. Analytical thinker with exceptional problem-solving and troubleshooting abilities. Effective mentor and leader, capable of guiding and inspiring junior engineers. Detail-oriented and process-driven, committed to delivering excellence in every project. Resilient and adaptable, able to multitask and manage shifting priorities in a fast-paced setting. The Team You’ll Be A Part Of: You will join a world-class team of verification engineers dedicated to delivering high-performance, reliable ASIC solutions. Our team values technical excellence, innovation, and collaboration. We work closely with architects, designers, and validation teams to ensure robust product delivery. As a senior member of the team, you will have the opportunity to influence verification strategies, lead technical initiatives, and mentor the next generation of engineering talent at Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Key skills with hand on :Design Verification, System Verilog ,SOC, SV -UVM, Testplan, Test bench, VCS, Verdi, Cadence, Simvision, jasper Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: • 6+ years of hands-on DV experience in SystemVerilog/UVM. • Must be able to own and drive the verification of a block / subsystem or a SOC. • Should have a track record of leading a team of engineers. • Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. • Experience in Tesplan and Testbench development, • Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. • Should be good with debugging and exposed to all aspects of verification flow including Gatesims • Must have extensive experience in verification of one or more of the following: o PCI Express or UCIe, CXL or NVMe o AXI, ACE or CHI o Ethernet, RoCE or RDMA o DDR or LPDDR or HBM o ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages o Power Aware Simulations using UPF • Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. • Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase. • Experience in SVA and formal verification is desirable (not a must) • Script development using Python, Perl or TCL is desirable (not a must)

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 3 -7 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: - Designing, developing, and troubleshooting core algorithms for compiler. - Collaborating with local and global teams to enhance runtime performance for verilog compiler. - Engaging in pure technical roles focused on software development and architecture. - Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions. The Impact You Will Have: - Driving technological innovation in chip design and verification. - Enhancing the performance and quality of simulation tools used globally. - Solving complex compiler optimizations problems to improve simulation performance. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: - Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: - Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Description The position involves design verification of next generation IP’s /SoC’s with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. Responsibilities: To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected Experience working on AMS Verification on multiple SOC’s or sub-systems Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites Developing and validating high-performance behavior models Verifying of block-level and chip-level functionality and performance Team player with good communication skills and previous experience in delivering solutions for a multi-national client Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. Ability to extract simulation results, capture in a document and present to the team for peer review Supporting silicon evaluation and comparing measurement results with simulations UVM and assertion knowledge would be an advantage Experience Level: 3-15 years in Industry , Work Location: Hyderabad , Bangalore. Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering Minimum Qualifications: Proficient in at least one of the following languages: Verilog, SystemVerilog, VerilogAMS. Strong understanding of analog circuits, digital design processes, and top-level integration. Basic knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a basic understanding of Python.

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments Responsibility- Primary responsibility includes I/O, Macro Characterization, EDA View generation (Functional, Electrical and Physical) & Full package validation. He/she needs to be in constant contact with IP design experts to understand the IP design (schematic, Layout) & IP specification (more electrical characteristics and functional aspect). Must have skills: Excellent understanding of digital design concepts and CMOS fundamentals. Ability to quickly comprehend the functional and electrical specifications of custom/full custom IPs. Proficient in IO/Standard cells/Memory characterization flow using industry-standard tools such as Kronos, Liberate, and Silicon Smart. Strong understanding of various formats of liberty files, including NLDM, CCS, and LVF. Skilled in custom layout and schematic design/updates. Experienced in IP physical model generation (LEF, sign-off GDS, CDL) and conducting validation checks (DRC, LVS, ERC) with debugging skills. Proficient in behavioral modeling using Verilog/SystemVerilog and testbench writing. Experience in IBIS (Input/Output Buffer Information Specification) modeling is a plus. Excellent team player who is disciplined, adaptable, and possesses strong communication skills. Qualification & Experience B. Tech / M. Tech – Electronics/VLSI Engineering 3 to 7 years of professional experience in EDA/CAD View generation domain. Prior ST experience even as intern is preferred. Skills CAD Design engineer,Standard Cell,Cmos

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills We are seeking an experienced HDL design/verification engineer to design, develop, and enhance the simulation capabilities within Lattice Radiant — Lattice Semiconductor’s official FPGA design tool. You’ll be part of the Lattice Software Radiant team working closely with the hardware developers and QA teams to support simulation flows, help validate new features and ensure seamless integration of simulation engines with Radiant’s toolchain. Key Responsibilities Enable and support simulation workflows for Verilog, VHDL, and SystemVerilog across various Lattice FPGA families Assist in diagnosing and resolving simulation issues reported by internal developers or users Validate and test simulation features, waveform viewers, and debug interfaces within Radiant Contribute to automation scripts and testbench generation tools Maintain simulation documentation, troubleshooting guides, and user tutorials Required Qualifications Bachelor’s or Master’s degree in Electronics Engineering, or related field Solid experience with hardware description languages (HDLs) and simulation tools (e.g., Modelsim, Synopsis VCS) Solid understanding of HDL simulation concepts: elaboration, scheduling, waveform generation Solid experience in EDA tool development or FPGA simulation frameworks Familiarity with Lattice Radiant Software, FPGA architectures, and configuration flows Industrial experience in similar field for > 5 years. Preferred Skills Strong analysis and debugging capabilities Excellent communication and cross-disciplinary collaboration skills What We Offer Direct impact on the evolution of FPGA development tools and methodology Competitive compensation and comprehensive benefits A highly collaborative and intellectually driven team environment Supportive cross-geo team environment and technical mentorship

Bangalore,Karnataka,India Job ID 768632 Grow with us We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What We Offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced design technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. What you will do Key Responsibilities: Develop ASIC IP blocks and subsystems, contributing to the advancement of 5G and 6G communication technology. Take full ownership of a design, whether at the block or subsystem level. Generate comprehensive documentation throughout the design lifecycle. Perform digital design and conduct all RTL sign-off checks. Continuously enhance and optimize design methodologies and processes. Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications. Work closely with verification engineers to review and refine verification plans. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 5+ years industry experience in ASIC design. Additional experience will allow placement at higher job levels. Strong Experience in/with: Understanding of ASIC technology, design environments, and methodologies. SystemVerilog RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions. The skills you bring Additional Requirements: Experience with Cadence and Synopsys front-end and middle-end design suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Expertise in low-power design, including specifying power intent using UPF or similar standards. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) What happens once you apply?

RTL/FPGA Design Engineer(Experienced). Exp : Min 3- 7 Years of Experience Job Description & Responsibilities RTL programming (Verilog/System Verilog or VHDL). Knowledge of complete FPGA Design Development flow. Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.) Functional verification using Verilog/System Verilog or VHDL. RTL Code Optimization to meet timings and fit on-chip resources. Support all phases of FPGA based product development activities. System Architecture Design. Testing and troubleshooting of hardware. Skills Requirements BE/B. Tech in Electronics/Electronics & Communication from a recognized university with a good academic record. ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record. Experience with Verilog/SystemVerilog or VHDL for design and verification. In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral. Should be able to develop the small blocks of IP from scratch and do basic functional verification. Should be familiar with protocols like SPI, I2C, UART and AXI. Understanding of standard/specification/application for IP design or system design. Knowledge of Altera Quartus II Tool, Questasim, Modelsim. Knowledge of Xilinx tools like ISE, and Vivado. Knowledge of Microsemi tools like libero. Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM and QSPI-NOR based Flash. Personal Competency Self-motivated to learn and contribute. Ability to work effectively with global teams. Able and willing to work in a team-oriented, collaborative environment. A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment. Proven analytical and creative problem-solving abilities. Passionate about writing clean and neat code that adheres to coding guidelines. (ref:hirist.tech)

As a Senior/Lead/Sr. Lead Design Verification Engineer at our company located in Bangalore or Hyderabad, you will play a crucial role in ensuring the verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need to have a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 4 years of hands-on experience in this domain. Your responsibilities will include utilizing your expertise in SystemVerilog and UVM to develop verification components like scoreboards, monitors, and sequencers. You will be required to have a strong understanding of digital design principles, verification methodologies, and simulation tools. Additionally, familiarity with protocol specifications and industry standards for DDR, PCIe, UCIe, or NVMe will be crucial for this role. Having experience with simulation tools such as VCS, ModelSim, or Questa will be an added advantage. You should also possess good debugging skills using tools like Waveform Viewers, Logic Analyzers, and protocol analyzers. Problem-solving skills, attention to detail, and the ability to work collaboratively are essential traits for this position. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, and proficiency in scripting languages like Python for automation purposes. Familiarity with FPGA-based verification platforms and hardware debugging tools will be beneficial in excelling in this role. If you are looking to join a dynamic team where you can leverage your skills in design verification and work on cutting-edge technologies, this position is ideal for you. Join us in our mission to push the boundaries of innovation and make a significant impact in the field of high-speed interface verification.,

Job Overview In Arm&aposs Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavor to deliver quality silicon we need to ensure all our sign-off checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improving methodologies, influencing EDA tools and building a knowledge base which will help with our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If youre interested in working with a team of collaborative and smart engineers in developing silicon that defines the future then, you belong in ARM! Responsibilities Setting up and running Logic Equivalence check which is of signoff quality. Analyzing low power results and signing off on the structural checks run using Conformal Low Power. Provide feedback to relevant teams to ensure successful closure of blocks on time. ECO is part of every silicon now a days and the engineer needs to own up generating functional ECO for quick closure Collaborate with RTL, Synthesis and PnR implementation team to successfully close on different hard macros Work with methodology team to improve the flow Develop automation using python/perl/tcl scripting to avoid repetitive tasks and thus improve your work life balance Supporting and enabling other sign-off team members to attain efficient and quality outcomes Required Skills and Experience Bachelors/Masters with 3-5 years of minimum experience in Logic Equivalence check (Formality / LEC) and Low power (VCLP / CLP) Values communication as a key medium to nurture learning, builds trust with others and solves sophisticated problems with dependencies. Strong understanding in RTL coding (SystemVerilog, Verilog & VHDL) and RTL for Synthesis Good understanding of the concepts related to Low power synthesis, place & route, DFT. Should be proficient in any of the scripting or automation languages such as Python, Perl, TCL, Sed or Awk. Nice To Have Skills and Experience Working on ARM CPU and GPU designs would be added value Experience working on generating functional ECO using EDA tools will add value In Return ARM is proud to be an equal opportunity employer. We are committed to fostering a culture of respect, inclusion, and fairness for all. We welcome applications from all individuals, regardless of race, ethnicity, gender, age, disability, sexual orientation, religion, or background. We believe that diverse teams drive innovation, and we work hard to ensure that all our employees can thrive in an environment built on mutual respect and equal opportunity. At ARM, you get to Learn and Innovate! Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [HIDDEN TEXT]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodation. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arms hybrid approach to working is centered around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [HIDDEN TEXT] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 3 -7 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: Designing, developing, and troubleshooting core algorithms for compiler. - Collaborating with local and global teams to enhance runtime performance for verilog compiler. - Engaging in pure technical roles focused on software development and architecture. - Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. - Enhancing the performance and quality of simulation tools used globally. - Solving complex compiler optimizations problems to improve simulation performance. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. Experience designing and implementing complex functional verification environments is required. Knowledge of protocols like PCIe, USB3/4, DP an added advantage. We’re doing work that matters. Help us solve what others can’t.

Category Engineering Hire Type Employee Job ID 12393 Remote Eligible No Date Posted 29/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 3 -7 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: - Designing, developing, and troubleshooting core algorithms for compiler. - Collaborating with local and global teams to enhance runtime performance for verilog compiler. - Engaging in pure technical roles focused on software development and architecture. - Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions. The Impact You Will Have: - Driving technological innovation in chip design and verification. - Enhancing the performance and quality of simulation tools used globally. - Solving complex compiler optimizations problems to improve simulation performance. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: - Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: - Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary: Join Qualcomm’s cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). You will work on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. A strong understanding of on-chip buses and bridges is essential to ensure seamless integration and performance across subsystems. Key Responsibilities: Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling. Perform power-aware verification using UPF/CPF and validate low-power design intent. Execute performance verification to ensure bandwidth, latency, and throughput targets are met. Preferred Skills & Experience: 2–15 years of experience in digital design and verification. Deep understanding of bus protocols and bridge logic, including hands-on experience with AXI, AHB, and APB. Experience with CPU subsystem verification and performance modeling. Familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be) is a plus. Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python). Experience with power-aware verification methodologies and tools (e.g., UPF, CPF). Familiarity with performance verification techniques and metrics. Exposure to tools like Clearcase/Perforce and simulation/debug environments. Strong analytical, debugging, and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science, or related field. Relevant experience in hardware design and verification. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

We are seeking a highly experienced Hardware Verification Engineer with extensive hands-on experience in block-level, IP-level, and SoC-level verification. You will leverage your proficiency in Verilog, SystemVerilog, and UVM-based testbenches, along with knowledge of industry-standard EDA tools, to ensure the robustness and functionality of complex hardware designs. This role requires strong problem-solving and communication skills, and an in-depth understanding of ARM AMBA protocols. Hardware Verification Engineer Roles & Responsibilities: Develop and execute comprehensive verification test plans for block-level, IP-level, and SoC-level designs. Create and maintain efficient UVM-based testbenches . Utilize Verilog and SystemVerilog for testbench development and assertion-based verification. Employ industry-standard EDA tools for simulation and debug to identify and resolve hardware design issues. Verify the functionality and performance of IPs for caches, cache coherency, memory subsystems, interconnects, and NoCs (Networks-on-Chip). Collaborate closely with design teams to understand architectural specifications and ensure verification coverage. Debug complex hardware and software interactions, contributing to root cause analysis. Potentially explore and apply formal verification techniques and emulation platforms . Ensure the quality and reliability of hardware designs prior to tape-out. Qualifications and Preferred Skills: Strong hands-on experience in block-level/IP-level/SOC-level verification . Proficiency in Verilog, SystemVerilog . Familiarity with industry-standard EDA tools for simulation and debug . Deep experience with UVM-based testbenches . Experience with modern programming languages like Python . Knowledge of ARM AMBA protocols such as AXI, APB, and AHB. Understanding of ARM CHI protocol is a plus. Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs. Experience with formal verification techniques, emulation platforms is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills. QUALIFICATION: BS, MS in Electrical Engineering, Computer Engineering or Computer Science.

You should have experience working with USRP N310/X310 (N3xx/X3x0) and possess a deep understanding of FPGA Architecture. Additionally, you must be proficient in writing your own RTL custom HDL or integrating IP components, including VHDL, Verilog, System Verilog, Vivado HLS, Xilinx IP, and Vivado Block Diagram. It is essential that you have developed RFNoC Blocks and have a good grasp of the USRP Hardware Driver (UHD). Your responsibilities will include creating custom FPGA logic in RFNoC Blocks, utilizing existing RFNoC Blocks library, and understanding the GNU Radio interface to RFNoC Block. Furthermore, you will be involved in FPGA debugging, hardware/software integration, and implementing appropriate coding styles for FPGAs while considering density and speed trade-offs. A thorough knowledge of XILINX ZYNQ 71xx/PL-KINTEX-7 based RFNoC architecture is crucial for this role. You will also be required to comprehend customer requirements, define architecture, and develop detailed designs. Strong communication skills and familiarity with Agile methodology are necessary for effective interaction with customers. In addition to the technical skills, the ideal candidate should hold a Bachelor's degree in Engineering or Technology (B.E./B.Tech.). Please note that we are accommodating a notice period of up to 30 days for this position.,