1205 Verilog Jobs - Page 6

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We Make Real What Matters. This is your role! Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and improve these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will cooperate with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds We seek a graduate with an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute Phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. We value sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. Knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a phenomenal teammate, resilient and candid, Enjoy learning new things and build knowledge base in new area. We’ve got quite a lot to offer. How about you? This role is based in Noida but you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. Show more Show less

Job Summary: Seeking a Senior DFT Engineer with 10+ years of experience adept in SOC DFT implementation. Job Responsibilities Develop and implement DFT strategies for advanced VLSI designs. Collaborate with design and verification teams to ensure DFT requirements are met. Perform scan insertion, ATPG pattern generation, and BIST (Memory and Logic) implementation. Perform DFT simulations and analyze results to ensure test coverage and quality. Debug and resolve DFT-related issues throughout the design process. Stay updated on industry trends and advancements in DFT methodologies. Mentor junior engineers and provide technical guidance as needed. Job Qualification Senior DFT engineer with 10+ years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, LBIST. The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Must have worked on one SoC at least, from start to end. Must be proactive, collaborative and detail-oriented capable of exercising independent judgment Strong expertise in Post Silicon Readiness (Pattern Generation) and Silicon Debug. The engineer with experience on debug and root cause the problem in simulation failures. BE/ME/B.Tech/M.Tech from reputed institutes Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills Show an engaged curiosity, a will to understand the mechanisms behind the effects, an eagerness to constantly learn and improve More information about NXP in India... Show more Show less

Hi All, Looking for DV - Verification Engineer with Pcie exp. Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols like PCie. Verification for complex IP’s and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol and Pcie. Please share your resume to jayalakshmi.r2@ust.com Regards, Jaya Show more Show less

Hi All, Looking for Design Verification Engineer with UVM and Verilog experience. Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IP’s related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IP’s and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol Please forward your resume to jayalakshmi.r2@ust.com Regards, Jaya Show more Show less

Senior Verification Engineer Location: Bangalore/Hyderabad Experience: 5+ years 1Must have very good System Verilog/UVM experience Must have expertise in PCI gen6 and CXL3.1or Ethernet bus protocols Have experience in IP/SoC Verification Expertise in AMBA/AXI bus protocols and ARM CPU Experience in developing functional verification environments including the components like monitors, checkers, scoreboards and assertions Experience in code and functional coverage Scripting Language (PERL/Python/Shell/Makefile) Must have good debugging and problem-solving skills Good to have GLS verification experience Educational Qualification: BE/ME or BTech /MTech Show more Show less

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance Job Description The position involves designing, developing and deploying UVM/C based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I3C, PWM. Responsibilities: Develop and track execution of chip level test planning to meet product requirements and established quality standards Lead a team to complete the pre-silicon verification of an SoC Execute and maintain chip level verification regressions. Triage and debug failing tests. Develop or update tests to satisfy the test plan requirements. Tests will be combination of directed (C tests), constrained random (UVM), and formal verification. Perform gate level verification across corners. Provide appropriate activity files for power analysis. Coordinate verification activities with a global team and the design lead. Provide succinct weekly status and drive action items to closure. Experience Level: 10-15 years in Industry Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering Minimum Qualifications: Develop and signoff on test plans and test cases Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture Strong knowledge of Verilog, System Verilog, UVM, C/C++ Experience in usage of assertions, constrained random generation, functional/code coverage. Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Very strong Analytical debugging skills Knowledge on C Based Testcases. Knowledge of SoC,Memory and Cache Architectures Knowledge on Low power designs and architectures Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Low-power implementation (UPF) Mixed Signal Real Number Modeling (RNM, Spice) Preferred Qualifications: Knowledge of high-speed interfaces like Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Show more Show less

Role: FPGA Engineer Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL. Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts. Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable. Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus. Strong analytical and problem-solving skills, with the ability to optimize designs for performance, power, and resource utilization. Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment.

Key Responsibilities: Perform block- and chip-level functional verification of complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs and subsystems. Create and execute detailed verification test plans based on specifications. Develop constrained-random and directed test cases and debug simulation issues. Conduct functional and code coverage analysis and drive coverage closure. Use RAL (Register Abstraction Layer) for register-level testing. Develop and validate SystemVerilog Assertions (SVA). Candidate Requirements: • Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields. • Experience: 6–10 years of relevant experience in ASIC/SoC design verification.

Title: Principal Engineer Design Enablement (GAN HEMT modeling) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction: GlobalFoundries is seeking a motivated, self-driven engineer to develop Compact models of HEMT devices, which are actively used by clients to design state-of-the-art IC design solutions. Your Job : The role requires a strong background in semiconductor device physics. The candidate should be familiar with the electrical behaviors of semiconductor devices (DC/low frequency, RF/high frequency, noise, mismatch, etc.), and the types of test structures that are needed to characterize them. The candidate should be able to apply his/her knowledge of semiconductor device physics in a practical compact model extraction scenario, such as being able to analyze and explain the trends in the data, being able to distinguish real trends from noise , associate various physical phenomena with the observed trends, submit electrical characterization requests, extract various compact modeling parameters, do various QA checks and submit the model for release. The candidate should also be able to do design and layout of test structures; be able to correlate device cross section with layout; do various kinds of simulations in Cadence ADE; be proficient in writing python scripts for doing model parameter extraction, data analysis and QA; have knowledge of industry standard compact model families and parameter extraction tools/methodologies; have knowledge of Verilog-A and be able to write Verilog-A models; and be able to field customer queries pertaining the model. Other Responsibilities: Apart from strong technical skills, the candidate should also possess excellent communication skills and be able to work across geographies and time zones. He/She should be self driven and self motivated to excel, innovate and solve problems. This position is based out of Bangalore. Required Qualifications : PhD with specialization in HEMT devices Years of Experience 0 #NCGProgramIND

Title: Principal Engineer Design Enablement (GAN HEMT modeling) About GlobalFoundries Introduction: GlobalFoundries is seeking a motivated, self-driven engineer to develop Compact models of HEMT devices, which are actively used by clients to design state-of-the-art IC design solutions. Your Job : The role requires a strong background in semiconductor device physics. The candidate should be familiar with the electrical behaviors of semiconductor devices (DC/low frequency, RF/high frequency, noise, mismatch, etc.), and the types of test structures that are needed to characterize them. The candidate should be able to apply his/her knowledge of semiconductor device physics in a practical compact model extraction scenario, such as being able to analyze and explain the trends in the data, being able to distinguish real trends from noise , associate various physical phenomena with the observed trends, submit electrical characterization requests, extract various compact modeling parameters, do various QA checks and submit the model for release. The candidate should also be able to do design and layout of test structures; be able to correlate device cross section with layout; do various kinds of simulations in Cadence ADE; be proficient in writing python scripts for doing model parameter extraction, data analysis and QA; have knowledge of industry standard compact model families and parameter extraction tools/methodologies; have knowledge of Verilog-A and be able to write Verilog-A models; and be able to field customer queries pertaining the model. Other Responsibilities: Apart from strong technical skills, the candidate should also possess excellent communication skills and be able to work across geographies and time zones. He/She should be self driven and self motivated to excel, innovate and solve problems. This position is based out of Bangalore. Required Qualifications : PhD with specialization in HEMT devices Years of Experience 0 #NCGProgramIND GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

: Arm s Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arms soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. Responsibilities: Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation. Required Skills and Experience : This role is for a Principal DFT Engineer with proven ability in Design for Test Experience coding Verilog RTL, TCL and/or Perl Proficient in Unix/Linux environments Core DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics Bachelors or Master s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field Nice To Have Skills and Experience : Familiarity with IEEE 1149, 1500, 1687, 1838 Synthesis & Static Timing Analysis Familiarity with SoC style architectures including multi-clock domain and low power design practices. Validated understanding of Siemens DFT tools Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug Experience with 2.5D and 3D test Ability to work both collaboratively on a team and independently Hard-working and excellent time management skills with an ability to multi-task An upbeat demeanor to working on exciting projects on the cutting edge of technology Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding! Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promise

About this Opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent.

Grow with us About this opportunity We are seeking a Senior FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Join our Team About this opportunity We are seeking a Senior FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 768496

JD : Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Job Description - Grade Specific JD : Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Skills (competencies) Verbal Communication

Develop RTL (Verilog/SV) per microarchitecture specs, integrate IPs, perform lint/CDC, support synthesis. Strong in digital design, AMBA (AXI/AHB), low-power (UPF), TCL/Python. Tools: DC, Genus, SpyGlass. Collaborate on debug & reviews.

Position: Lead RTL Design Engineer (ASIC/FPGA) Location: Bangalore Experience: 7+ years Senior / Lead Level Role Overview Were seeking a proactive Lead RTL Engineer to define micro-architectures, implement robust RTL, guide integration, and collaborate across ASIC and FPGA domains. You will architect complex subsystems and mentor a high-performing team. Key Responsibilities Micro-architecture & Specifications: Create block-level design docs & detailed RTL micro-architecture for highcomplexity IP/subsystems. RTL Coding & Review: Develop clean, synthesizable RTL in Verilog/SystemVerilog/VHDL. Ensure code quality via lint/CDCC/static timing checks. Integration & IP Subsystems: Integrate with SoC/FPGA subsystems—protocols like AMBA/AXI, interconnects, memory, serial interfaces. Synthesis & Timing Closure: Lead flows using Design Compiler, Primetime, STA tools to meet timing and area goals. Verification & Debug: Coordinate with verification leads, support testbench development, and debug RTL—functional, wavebased, simulation. Leadership & Mentorship: Mentor engineers, lead reviews, steer integration, and liaise across RTL, verification, physical design, and architecture teams. Toolchain & Scripting: Script for automation (Tcl, Python, Perl, Shell); manage version control (e.g. Perforce, Git) . Innovation & Best Practices: Drive RTL design best practices, stay current with EDA tools, lowpower (UPF), CDC, linting, and continuous improvement. Required Qualifications Bachelor’s/Master’s in EE/CE or similar. 7+ years in RTL for ASIC/FPGA, +3 years in a leadership role. Expert in Verilog/SystemVerilog/VHDL, microarchitecture, FSMs, datapaths, CDC. Experienced with SoC/IP integration—AXI, AHB, APB, PCIe, USB, Ethernet, DDR, etc. Proficient with synthesis, STA, CDC, lint tools, DFT flows. Solid scripting with Tcl/Python/Perl/Shell and version control systems. Strong communication, documentation, team leadership, and cross-team collaboration skills. Preferred Skills FPGA prototyping and hardware bring-up expertise. Low-power methodologies (UPF, power gating). ASIC methodology experience (synthesis, timing, DFT, PPA closure). Familiarity with UVM verification, formal methods. Integration experience with high-speed or accelerator IP (NoC, memory controllers, etc.). What You’ll Get High-impact leadership in advanced RTL design for ASIC/FPGA cutting-edge chips. Opportunity to mentor and build a top-tier RTL team. Collaborative culture working with architecture, verification, PD, and system teams. Learning, ownership, and visibility across end-to-end chip delivery.

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments JD:- Asic RTL Design: Digital Design Knowledge RTL coding – System Verilog/Verilog/VHDL SoC integration experience is preferred CDC, Linting knowledge Synthesis, STA, DFT, Layout reviews experience Skills Rtl Coding,SOC integration,CDC Show more Show less

This role is for one of Weekday's clients Min Experience: 4 years Location: Bengaluru JobType: full-time Requirements About the role Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across all regimes, enabling end-users to gain actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities, aligned with the key principles of situational awareness: perception (data collection) , comprehension (data processing) , and prediction (analytics) . This holistic approach empowers Digantara to monitor all Resident Space Objects (RSOs) in orbit, thereby fostering comprehensive domain awareness. Digantara seeks a highly skilled Senior Embedded Software Engineer to design and develop embedded software solutions tailored specifically for real-time image processing. You will leverage your expertise to enable the development of state-of-the-art embedded software with applications such as tracking objects from both space and the ground. Why Us? Be part of a collaborative and innovative environment where your ideas and skills make a real difference to the entire space realm Push the boundaries with hands-on experience, greater responsibilities, and rapid career advancement Competitive incentives, galvanizing workspace, blazing team—pretty much everything you have heard about a startup Responsibilities Design, develop, and implement embedded software for real-time image processing for satellite payload applications Translate and optimize image processing algorithms to FPGA/SoC platforms to achieve low latency and high throughput Collaborate with system-level designers and hardware designers, generate software functional requirements and architecture, and ensure seamless integration of software and hardware Collaborate effectively with cross-functional teams to conceptualize, design, and implement optimal embedded software solutions for image processing Define and implement interface and communication protocols for data handling between the satellite payload and bus systems Develop clean, well-structured, maintainable code and execute comprehensive testing according to space industry standards (e.g., the ECSS software engineering standard) Implement rigorous software quality assurance practices, including static analysis, code coverage analysis, and other verification techniques Develop efficient embedded software for high-performance embedded systems with the ARM Cortex processor architecture Leverage AMD-Xilinx/Microchip EDA tools (e.g., Vivado/Vitis IDE, Libero SoC design suite) to develop efficient embedded software solutions Troubleshoot and resolve embedded software defects and hardware interface issues Required Qualifications B.Tech/B.E in Electronics Engineering or M.Tech/M.E or PhD degree in Embedded Systems/VLSI 4+ years of experience in Embedded software design and development, with a strong focus on image processing and experience in handling communication protocols Strong proficiency in bare-metal and RTOS programming for embedded systems, with expertise in real-time scheduling, interrupt handling, and device drivers Proven ability to optimize embedded software implementation, including code optimization, memory management, and power efficiency techniques Proficiency in Embedded C and C/C++ programming languages Strong understanding of data communication protocols such as I2C, UART, SPI, CAN, Gigabit Ethernet, LVDS, RS422, etc Working knowledge of software configuration management tools and defect tracking tools Preferred Skills Prior experience in embedded software implementation, particularly in areas such as satellite imaging payloads or ground-based imaging systems, is highly preferred Working knowledge of FPGA/SoC-based embedded systems designed for image processing applications is highly valued Experience in hardware-related programming of FPGA interfaces and high-level synthesis Knowledge of implementing fault-tolerant embedded systems for satellite applications Familiarity with digital image processing and implementation Experience in the Python programming language and knowledge of Verilog/VHDL Experience with various camera interfaces, including USB3, CoaXPress, CameraLink, PCIe, and Gigabit Ethernet General Requirements Ability to work in a mission-focused, operational environment Ability to think critically and make independent decisions Interpersonal skills to enable working in a diverse and dynamic team Maintain a regular and predictable work schedule Writing and delivering technical documents and briefings Verbal and written communication skills, as well as organizational skills Travel occasionally as necessary Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary General Summary: Bachelors /Masters degree in Engineering Relevant experience of 2-12 yrs in any of the mentioned domain - Design/Verification/ Implementation Will be working on cutting-edge Wireless Technology (IEEE 802.11) team. Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Design You will be responsible for developing HW blocks (IP design), conduct High/Mid/Low level Design review and delivery IP to Subsystem team for making complex SoCs. You will be a critical part of the WLAN subsystem, contribute to IP design, sign-off the core to the SOC design team. Strong communication skills to work with design teams worldwide Verification Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C As a design verification engineer you will work on developing IPs catering to upcoming Wifi standards like 802.11bn and beyond. You will have opportunity to contribute to the life cycle of the technology right from IP specification, till productization/customer deployments, leveraging your verification, pre and post silicon debug expertise. Implementation Candidate will be responsible for next generation WLAN hardmacro implementation Extensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO Extensive experience in UPF based power intent and synthesis Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3064190 Show more Show less

Siemens EDA, a part of Siemens Digital Industries Software, is a global technology leader in electronic design automation. Our technologies enable companies around the world to develop new, highly innovative electronic products faster and more cost-effectively. Our customers use our solutions to push the boundaries of technology to deliver better products in the increasingly complex world of chip, board, and system design. Listener, Understander, Doer. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to tackle any technical problem. You are a competent adviser, team player, and make things possible. Unsolvable is a foreign term, and you dont do unfair. Your focus on the customers needs makes you an invaluable partner. When you join our team, you will reach one hundred percent in your career. As an integral part of the technical team, you will contribute to Siemens EDA by increasing productivity and customer satisfaction Siemens EDAs Verification platform. This is an ambitious position that will assist in growing Siemens's business in India. Your new role: results-oriented and futuristic You will be working collaboratively with customers as well as customer support and engineering teams to optimally deploy Siemens EDAs Questa products and services. Youll fosters a climate conducive to help grow customer satisfaction with Siemens tools by helping them successfully deploy new flows and methodologies. Optionally mentor and lead a team of application engineers, supervise and guide them on the accounts and engagements that they are working on. Youll be working with customers with varying design styles and methodologies to craft the most effective technical solutions. Youll provide key expert advice and contribute to technical campaigns in other regions. Identify and qualify potential new business opportunities and work the account teams to build an engagement plan. Work with Account Managers and the world-wide teams for forming strategies and driving Siemens tools for customer projects to enable business success for Siemens EDA. Become a trusted advisor to your customers. Will have moderate travel within India and abroad We are not looking for superheroes, just super minds Youre a Graduate / Post Graduate (Bachelors/Masters) Electronics and Communication (E&C) / Electrical / Telecom Engineering / Computer Engineering with 4 - 10 years of meaningful experience in Digital design and Clock Domain Crossing or Lint EDA tools. Youve solid understanding on VHDL/Verilog, SystemVerilog and Assertions. Well versed with Multiple Clock and Reset Domains and Asynchronous clock or reset domain crossing verification ( Clock Domain Crossing - CDC & Reset Domain Crossing - RDC ) on designs Expertise in CDC tools like Questa/0in CDC, Spyglass or VC- CDC, or other CDC products is expected Expertise in Formal Verification products like Questa Formal, Jasper or any other Formal products is a plus Low power verification techniques using UPF and CPF is a plus Exposure to static timing analysis (STA) flows involving SDC is a plus

Looking for Siemens EDA Ambassadors- QuestaSim (Simulation) R&D team (strong AI/ML background) This is your role In this role, you will, craft and develop AI/ML-driven algorithms and solutions to improve simulation tools' performance and capabilities. Contribute to building state-of-the-art engines and components, integrating machine learning techniques into simulation and verification workflows. Contribute to the development and improvement of production-quality components, algorithms, and engines while supporting and improving existing codebases. Solve complex, open-ended problems in collaboration with a senior group of engineers in a fast-paced and multifaceted environment. Apply technical expertise in AI/ML frameworks, data-driven problem solving, and traditional simulation technologies to achieve project milestones. Stay self-motivated, disciplined, and focused while driving innovation within the team. Required Qualifications We are seeking a graduate with Bachelors or Masters degree in Computer Science, Artificial Intelligence, Electrical Engineering, or a related technical field from an accredited institution. We value your experience with conceptualizing, defining, architecting, and implementation of an open-ended problem scope or new insights. Hands-on experience with AI/ML techniques, including supervised and unsupervised learning, neural networks, and reinforcement learning. Strong proficiency in programming languages like C/C++ and Python, along with strong foundations in algorithms and data structures. Knowledge of machine learning and deep learning frameworks. Strong understanding of Compiler Concepts, Optimizations, and parallel computing. Experience working on UNIX and/or LINUX platforms. Excellent problem-solving and analytical skills. Proven track record to work independently, take ownership of tasks, and deliver results A plus! Basic knowledge of Digital Electronics and concepts related to SystemVerilog, Verilog, and VHDL. Exposure to Simulation technologies or Formal-based Verification methodologies is a plus!

Facebook is hiring ASIC Design Engineers within our Infrastructure organization. We are looking for experienced individuals with knowledge that span one or more of the key areas required to build successful complex SoC and IP for data center applications. ASIC Engineer, Design Responsibilities: Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, & Power Optimization Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power Minimum Qualifications: 15+ years of silicon development experience Track record of first-pass success in ASIC Development Experience with Verilog or System Verilog Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs, OR Experience in SoC Micro-architecture, Design and Integration, OR Implementation, Power methodology development Experience working across multiple projects Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Preferred Qualifications: Experience in data path development Experience in CPU, NOC, Memory and Peripheral Subsystems Experience in HLS Experience with Synthesis, Timing Closure and Formal Verification Methodology Experience with Power Analysis and Optimization Experience with scripting languages (TCL, Python, Perl, Shell-scripting) About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Show more Show less

Sr.Lead Silicon Design Engineer - FPGA Design Hyderabad, India Engineering 66386 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be implemented and verified Build Requirements Spec, Design spec, test plan and test spec documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to implement the new features and write the new feature tests and any required changes to the test environment Debug test failures to determine the root cause; work with other RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Minimum of 15 years of design and development experience, preferably in a customer facing role Minimum of 10 years of experience in FPGA VHDL and/or Verilog design, AMD technology and tools, FPGA verification and test Experienced in analysing customer requirements, effort estimation and committing a schedule for delivery Interaction with Architects, other RTL engineers and SW engineers to define system level requirements and usecases Leading a group of RTL engineers to deliver on customer commitments Experienced with Verilog, System Verilog, and C programming Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Developing UVM based verification frameworks and testbenches, processes and flows Experience in HW testing, including working with test equipment, logic and traffic analyzers, test generators, etc. Experience in designing complex systems involving one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, and shell are preferred. ACADEMIC CREDENTIALS: Top class Bachelors or Master's degree in Electronic Engineering Track record of high academic achievement #LI-PS1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Lead Silicon Design Engineer - FPGA Design Hyderabad, India Engineering 66384 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be implemented and verified Build Requirements Spec, Design spec, test plan and test spec documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to implement the new features and write the new feature tests and any required changes to the test environment Debug test failures to determine the root cause; work with other RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Minimum of 8 years of design and development experience, preferably in a customer facing role Minimum of 5 years of experience in FPGA VHDL and/or Verilog design, AMD technology and tools, FPGA verification and test Experienced with Verilog, System Verilog, and C programming Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Developing UVM based verification frameworks and testbenches, processes and flows Experience in HW testing, including working with test equipment, logic and traffic analyzers, test generators, etc. Experience in one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: Top class Bachelors or Masters degree in Electronic Engineering Track record of high academic acheivement #LI-PS1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Responsibilities: Lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback. (20%) Ensure the definition and implementation of test and verification plans. (20%) Collaborate with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements.(10%) Monitor and analyse coverage reports to ensure thorough verification. (10%) Identify and resolve verification issues and bugs, ensuring timely project delivery. (10%) Continuously improve verification processes, methodologies, and tools. (10%) Manage project schedules, resources, and deliverables to meet deadlines. (10%) Oversee the writing and debugging of System Verilog assertion.(10%) Minimum Qualifications: 8+ years of relevant experience in SOC verification. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design verification and team management. Proficiency in System Verilog and assertion-based verification. Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (e.g., VCS, Questa Sim). Experience with SoC design verification. Knowledge of HVL methodology (UVM/OVM) with the most recent experience in UVM. Experience with formal verification. Experience taping out large SoC systems with embedded processor cores. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification. Excellent problem-solving skills and attention to detail. Desired Qualifications Experience in wireless SoC design and verification. Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation. Familiarity with version control systems (e.g., Git).