Lead RTL Design Engineer

Job Description

Position: Lead RTL Design Engineer (ASIC/FPGA) Location: Bangalore Experience: 7+ years Senior / Lead Level Role Overview Were seeking a proactive Lead RTL Engineer to define micro-architectures, implement robust RTL, guide integration, and collaborate across ASIC and FPGA domains. You will architect complex subsystems and mentor a high-performing team. Key Responsibilities Micro-architecture & Specifications: Create block-level design docs & detailed RTL micro-architecture for highcomplexity IP/subsystems. RTL Coding & Review: Develop clean, synthesizable RTL in Verilog/SystemVerilog/VHDL. Ensure code quality via lint/CDCC/static timing checks. Integration & IP Subsystems: Integrate with SoC/FPGA subsystems—protocols like AMBA/AXI, interconnects, memory, serial interfaces. Synthesis & Timing Closure: Lead flows using Design Compiler, Primetime, STA tools to meet timing and area goals. Verification & Debug: Coordinate with verification leads, support testbench development, and debug RTL—functional, wavebased, simulation. Leadership & Mentorship: Mentor engineers, lead reviews, steer integration, and liaise across RTL, verification, physical design, and architecture teams. Toolchain & Scripting: Script for automation (Tcl, Python, Perl, Shell); manage version control (e.g. Perforce, Git) . Innovation & Best Practices: Drive RTL design best practices, stay current with EDA tools, lowpower (UPF), CDC, linting, and continuous improvement. Required Qualifications Bachelor’s/Master’s in EE/CE or similar. 7+ years in RTL for ASIC/FPGA, +3 years in a leadership role. Expert in Verilog/SystemVerilog/VHDL, microarchitecture, FSMs, datapaths, CDC. Experienced with SoC/IP integration—AXI, AHB, APB, PCIe, USB, Ethernet, DDR, etc. Proficient with synthesis, STA, CDC, lint tools, DFT flows. Solid scripting with Tcl/Python/Perl/Shell and version control systems. Strong communication, documentation, team leadership, and cross-team collaboration skills. Preferred Skills FPGA prototyping and hardware bring-up expertise. Low-power methodologies (UPF, power gating). ASIC methodology experience (synthesis, timing, DFT, PPA closure). Familiarity with UVM verification, formal methods. Integration experience with high-speed or accelerator IP (NoC, memory controllers, etc.). What You’ll Get High-impact leadership in advanced RTL design for ASIC/FPGA cutting-edge chips. Opportunity to mentor and build a top-tier RTL team. Collaborative culture working with architecture, verification, PD, and system teams. Learning, ownership, and visibility across end-to-end chip delivery.