1318 Verilog Jobs - Page 13

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.

Infrastructure Specialists at IBM are the backbone of our strategic initiatives to design, code, test, and provide industry-leading solutions that make the world run today - planes and trains take off on time, bank transactions complete in the blink of an eye and the world remains safe because of the work our software developers do. Whether you are working on projects internally or for a client, software development is critical to the success of IBM and our clients worldwide. At IBM, you will use the latest software development tools, techniques and approaches and work with leading minds in the industry to build solutions you can be proud of. Roles & Responsibilities: Develop precise, safe automation to deploy, configure, and maintain a large fleet of network infrastructure Develop guardrails and automated tests to monitor fleet health Develop tight processes that manage security concerns and compliance at speed Required education Bachelor's Degree Required technical and professional expertise 8+ years of strong, deep knowledge of Unix based computer operating system + system administration skill 8+ years of application development experience in a language such as C#, Java, Python, Ruby, C++, GoLang, or Nodejs Advanced scripting abilities and enterprise scale automation experience Excellent oral and written communication Preferred technical and professional experience Experience developing automated testing Experience with Ansible, Puppet, Chef, or other infrastructure configuration platform Knowledge of networking concepts and network devices

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Job Title: VLSI Faculty Location: Kochi, Kerala, India Job Type: Full-time Job Summary: We're looking for a highly motivated and knowledgeable VLSI Faculty to teach and develop curriculum related to VLSI design, including digital design, verification, and front-end design. The ideal candidate will have a strong academic background, excellent teaching and communication skills, and industry experience in VLSI design. Responsibilities: 1. Teach VLSI-related courses, including digital design, verification, and front-end design. 2. Develop and update curriculum related to VLSI design. 3. Conduct research and publish scholarly articles in the field of VLSI design. 4. Supervise and mentor students in academic and research projects. 5. Participate in departmental and institutional meetings and committees. 6. Ensure compliance with institutional policies, procedures, and quality standards. Requirements: 1. Master's in VLSI Design, Electronics Engineering, or a related field. 2. Minimum 1 year of teaching experience in VLSI design or a related field. 3. Industry experience in VLSI design, including proficiency in Verilog, SV, Digital, UVM, and front-end design. 4. Strong knowledge of VLSI design concepts, including digital design, verification, and front-end design. 5. Excellent teaching, communication, and interpersonal skills. 6. Ability to work in a fast-paced environment and prioritize multiple tasks. Job Type: Full-time Pay: ₹25,000.00 - ₹40,000.00 per month Benefits: Paid time off Schedule: Day shift Experience: VLSI: 1 year (Required) Work Location: In person

The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Educational Qualification: Bachelor major in electronics, embedded programming, ECE, EEE. Key Requirements: Experience in ASIC/FPGA verification using System Verilog. Develop and sign off on test plans and test cases. Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. Experience in AMBA AHB/AXI/APB based IPs design/verification. Experience in usage of assertions, constrained random generation, functional and code coverages. Experience in FPGA design and FPGA EDA tools will be a plus. Experience in scripting, such as TCL, Perl, Bash and python to automate the verification methodologies and flows. Able to build and set up scalable simulation / verification environments.

Hi, Greetings from EWarriors Tech Solutions. We are hiring for the below position: Role: Sr/Lead Design Verification Engineer Location: Siruseri, Chennai (Onsite – 5 Days) Experience: 6+ Years Notice: Immediate to 15 days Key Responsibilities: Perform functional verification at block and chip level for complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs or subsystems. Develop and execute detailed verification test plans based on design specifications. Write directed and constrained-random test cases; debug simulation failures. Perform coverage analysis (functional and code) and drive closure. Work with RAL (Register Abstraction Layer) to verify register-level functionality. Develop and validate assertions (SVA) for protocol and functional correctness. Collaborate closely with RTL, DFT, and GLS teams to ensure alignment across design phases. Participate in multiple tape outs , ensuring verification quality and delivery. Required Skills: Strong hands-on experience with System Verilog and UVM methodology . Solid knowledge of SoC/ASIC architecture and verification lifecycle. Hands-on experience in writing testbenches, stimulus, checkers, monitors, and scoreboards . Strong debugging skills using simulation tools like VCS , Questa . Experience with functional and code coverage . Familiarity with Register Abstraction Layer (RAL) modeling and verification. Excellent analytical and problem-solving skills. Strong communication and teamwork abilities. Candidate Requirements: Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields. Experience: 6–10 years of relevant experience in ASIC/SoC design verification. Must have contributed to at least two one or more successful tapeouts . If interested, kindly share the resumes to *bharathi@ewarriorstechsolutions.com* or contact @8015568995. Job Type: Full-time Pay: ₹1,200,000.00 - ₹1,500,000.00 per year Schedule: Day shift Morning shift Experience: SOC: 4 years (Preferred) ASIC: 4 years (Preferred) Register Abstraction Layer (RAL): 3 years (Preferred) Total work: 6 years (Preferred) System Verilog: 5 years (Preferred) UVM: 5 years (Preferred) VCS/Questa: 4 years (Preferred) Work Location: In person

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad ROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans. Relevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU sub-systems. Deep understanding and knowledge of verification methodologies, flows and quality metrics The incumbent will be responsible for executing complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews, and close tracking of technical as well as management aspect ESSENTIAL SKILLS & EXPERIENCE At-least 4 years of experience in System Verilog HVL. At-least 3 year of experience in OVM/UVM/VMM/Test Harness. Hands on experience of developing assertion, checkers, coverage and scenario creation. Must have executed at-least 1 SoC Verification project Experience in developing test and coverage plan, Verification environment and validation plan. Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required. EDUCATION BACKGROUND B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering. Show more Show less

JOB DESCRIPTION, ROLE & RESPONSIBILITES POSITION TITLE: Technical Lead – ASIC Design Verification LOCATION: Hyderabad/Bangalore/Chennai/Ahmedabad POSITION SUMMARY The candidate should have direct and first-hand experience working in managing 4 -10 member engineering team – and servicing clients in Project (ODC) based execution model as well as Staffing (Hyderabad Onsite requirements). ROLE & RESPONSIBILITIES · Incumbent will be responsible for Architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to various customers products · Incumbent will lead of an IP Verification team and provide technical leadership to the Design Verification team as a whole · Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members. · Must lead management and customer reviews for multiple projects · The specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification objective. · Develop/modify scripts to automate the verification process. · Maintain and extend assertion libraries, including support for both simulation and FV. · Developing verification environment including environment assumptions, assertions, and cover properties in context of the verification plan ESSENTIAL SKILLS & EXPERIENCE · Minimum 6 years of experience in System Verilog HVL. · Minimum 6 year of experience in OVM/UVM/VMM/Test Harness. · Hands on experience of developing assertion, checkers, coverage and scenario creation. · Must have executed at-least 2 to 3 SoC Verification projects · Experience in developing test and coverage plan, Verification environment and validation plan. · Knowledge of at-least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required. · Review and Audit participation. · At-least 1 year of experience in handling team of 5 to 10 engineers. · Define/derive Scope, Estimation, Schedule and Deliverables of proposed work. · Assure compatibility of resources, tools, platform · Work with customers through acceptance of deliverables. · Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members. Please note that this is a Work from Office Job and incumbent must have willingness and experience of leading and mentoring junior engineers. EDUCATION BACKGROUND · B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering. ABOUT eInfochips (An Arrow Company): eInfochips, an Arrow company (A $30B, NASDAQ listed (ARW); Ranked #102 on the Fortune List), is a leading global provider of product engineering and semiconductor design services. 25+ years of proven track record, with a team of over 2500+ engineers, the team has been instrumental in developing over 500+ products and 40M deployments in 140 countries. Company’s service offerings include Silicon Engineering, Embedded Engineering, Hardware Engineering & Digital Engineering services. eInfochips services 7 of the top 10 semiconductor companies and is recognized by NASSCOM, Zinnov and Gartner as a leading Semiconductor service provider. Show more Show less

Position: DFT Engineer (ASIC) Experience: 2 to 8 years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies . Show more Show less

Location : Bengaluru (preferred), Hyderabad, Kochi The ASIC Front-End Head is responsible for leading the front-end design team, ensuring high-quality Application-Specific Integrated Circuit (ASIC) designs, and driving innovation in digital chip development . This role requires expertise in RTL design, verification, synthesis, and architecture development , along with strong leadership and strategic planning skills. Key Responsibilities Technical Leadership: Define and implement best practices for front-end ASIC design , ensuring efficiency and performance. Architecture & Design: Oversee the development of digital circuits , including RTL coding, synthesis, and timing analysis. Verification & Validation: Ensure robust design verification methodologies using tools like UVM, SystemVerilog, and simulation frameworks . Cross-Team Collaboration: Work closely with back-end design, physical design, and fabrication teams to optimize chip performance. Innovation & R&D: Stay updated with emerging semiconductor technologies and drive research initiatives. Mentorship & Team Development: Guide and mentor engineers, fostering a culture of learning and technical excellence. Technical Project Management: Oversee front-end development timelines, ensuring timely delivery of high-quality designs. Required Qualifications Education: Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a related field . Experience: 15+ years in ASIC front-end design , with a proven track record of successful projects. Technical Skills: Expertise in HDLs (Verilog, VHDL), synthesis tools, timing analysis, and low-power design techniques . Leadership & Communication: Ability to lead teams, manage projects, and communicate effectively with stakeholders. Problem-Solving: Analytical mindset with a passion for optimizing digital designs for performance and efficiency. Show more Show less

Role overview and responsibilities: We are seeking experienced and motivated Senior Embedded Systems Design Engineers to join our dynamic Avionics/Hardware department. In this role, you will be instrumental in supporting design and testing activities for all embedded systems for spacecraft and ground station avionics. You will be involved in large SoC project for new satellite products, contributing across all phases of the design process from concept to the delivery of a fully functional system. Key responsibilities include, but are not limited to Design and implement microcontroller and FPGA-based digital circuits and systems, demonstrating proficiency in architectures, logic design, and hardware description languages (HDLs) such as VHDL or Verilog. Develop and optimize hardware design as well as firmware, ensuring efficient and reliable configurations and functionalities. Collaborate with hardware and software engineers to integrate designs into larger systems, ensuring seamless interaction with other components like processors, memory, and peripherals. Test and debug FPGA designs to meet functionality, performance, and reliability standards, utilizing simulation tools and hardware debugging equipment. Apply a strong foundation in electronics or physics, including understanding analog and digital circuits, signal processing, and system-level design. Work effectively in multi-disciplinary teams on fast-paced projects, fostering collaboration with colleagues from hardware, software, and system engineering domains. Utilize high-level synthesis tools and methodologies to convert high-level descriptions (e.g., C/C++) into FPGA designs, enhancing the design process. Stay adaptable and committed to continuous learning, as FPGA design is an ever-evolving field. Candidate Requirement At least 5-7 years of experience in FPGA design, with a proven track record of designing and implementing microcontroller and FPGA-based digital circuits and systems. Expertise in developing and optimizing firmware for embedded devices. Strong ability to collaborate with hardware and software engineers for system integration. Proficiency in testing and debugging embedded system designs to ensure they meet functional and performance standards. In-depth knowledge of design principles, with a focus on multi-disciplinary teamwork in fast-paced project environments. Strong understanding of the interaction between core device, software, and hardware design disciplines. Familiarity with high-level synthesis tools and techniques is a distinct advantag Familarity with signal integrity and power integrity analysis for high speed PCB designs. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly experienced and motivated professional with a solid background in SoC RTL Design. With over 12 years of experience, you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development. You possess a deep understanding of design concepts, ASIC flows, and stakeholder management. Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints. You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables. Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently. What You’ll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys’ reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You’ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years’ experience in SoC RTL Design. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive leader with excellent managerial skills. A team player who can mentor and guide engineers. An effective communicator who can interact with customers and stakeholders. A problem-solver with a keen eye for detail. An innovator who continuously seeks to improve processes. The Team You’ll Be A Part Of: As part of the System Solutions Group (SSG), you will lead a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Engineer Location : Hyderabad Work Type: Onsite Job Type: Full time Job Description: Design, implementation, test, integration, and delivery of system level digital designs for FPGA blocks timing verification Perform task of debugging design timing related issues on different FPGA families Perform the work of manifold segmentation of the FPGA designs. Run internal scripts for performance testing and update scripts when necessary Required skill Basic STA knowledge along with tools like Vivado. Experience on FPGA platforms like AMD(XILINX)/Altera. Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs Experience in scripting language like perl, python and tcl Working experience on Linux. Ensure to complete design and timing verification tasks within allotted timelines. Ability to work individually and in a team TekWissen® Group is an equal opportunity employer supporting workforce diversity. Show more Show less

Design Verification Engineer (3-7 years’ experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 3-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years’ experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement Design Verification Engineer (Senior Level - 10+ years’ experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions Show more Show less

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Bangalore / Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Principal IP/RTL Design Engineer for Ethernet Switch Bangalore / Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Design Verification Manager Hyderabad www.Sevyamultimedia.com About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Design Verification Manager We need an experienced DV lead/manager to verify IP/SoC using System Verilog/UVM Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 7-12 years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Role Description Role Proficiency: Provide leadership to a project with appropriate technical options and well suited design standards for embedded system product development system level validation and performance optimization strategies. Outcomes Design develop and implement system level specifications. Develop highly optimized secured code debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP owners product (HW & SW) architects for design and debugging as per the project needs. Prepare Release Notes and participate in release strategies. Mentor lead and manage Developers I II III – Embedded Software Engineers based on project needs Identify and recommend appropriate tools (SW & HW) for the project. Developing utilizing various debug validation tools and/or methodologies to implement Development and validation plans Create share best practices and lessons learned with the team. Optimises efficiency cost and quality. Influence and improve customer satisfaction Set FAST goals for self/team and also provide feedback to FAST goals of team members Measures Of Outcomes Adherence to embedded design process and standards Quick turnaround on multiple alternative solutions determining the most suitable Number of technical issues uncovered during the execution of the project Number of review feedback post Software Lead II review based on project SLA Number of design and test defects post-delivery based on project SLA Quick turnaround on defect fixing for design and tests based on project SLA Adherence to testing methodologies and compliance process Adherence to project schedule / timelines Deploy Innovation techniques and publish white paper Team management and productivity improvement as per Project SLA. Requirement Outputs Expected: Lead requirement engineering; collaboration with internal and external customers to understand their needs Design Embedded design architecture/LLD and linking to requirements Develop Design the embedded SW and code as per design patterns coding standards templates and checklists. Develop automated tools or scripts for the validation environment. Test Analysis and testing of prototypes validate the designed software document the analysis and test results Document Create documentation for one's own work and contribute to creation of design HLD LLD/architecture for component/system software/ application diagnostics and test results Status Reporting Report status of tasks assigned; comply with project related reporting standards/process Quality Lead design reviews add value take responsibility for the design and overall quality of the embedded software Release Adhere to release management process for circuit simulation design schematics board files Compliance Adhere to embedded software design regulatory and test compliance Estimate Estimate time effort resource dependence for one's own work and for projects' work. Accurately define and document the technical side of the project schedule with estimates and identified risks Interface With Customer Clarify requirements and provide guidance to development team. Present design options to customers and conduct product demos Manage Project Manage delivery of embedded software and manage requirement understanding and effort estimation. Manage Team Set FAST goals and provide feedback. Understand aspirations of team members and provide guidance opportunities etc. Ensure team is engaged in project Manage Defects Perform defect RCA and mitigation. Identify defect trends and take proactive measures to improve quality Manage Knowledge Consume project related documents and specifications. Review the reusable documents created by the team Skill Examples Ability to create Embedded C Program Development for system level. Capability in creating and executing one or more of the following domains: Storage/connectivity/Media/graphics/boot/clusters/infotainment/ADAS Ability to do C++ programming (OOP) Assembly programming skills Ability to handle OS Scheduler Pre-emptive Round robin & Cooperative scheduling related work Ability to handle SW development in area of CAN Diagnostics Vehicle Functions etc. Aptitude in Networking protocols such as CAN LIN etc Ability to select right IoT & IO protocols as per problem statement. Ability to do Unit Testing (Tessy & RTRT) using appropriate Integration Testing Tools Ability to define and execute test cases with techniques (White Box and Black box) Ability in Closed loop LabCar INCA or similar tools Capacity to configure GDT framework. Ability to adhere to software quality standards (MISRA PCLINT QAC). Ability to debug using embedded tools Ability to do automation and configure Simulation Tools. Proactively ask for and offer help Ability to work under pressure determine dependencies risks facilitate planning and handle multiple tasks. Build confidence with customers by meeting deliverables in time with quality. Estimate effort time resources required for developing / debugging features / components Make decisions on appropriate of the Software / Hardware’s. Strong analytical and problem-solving abilities Knowledge Examples Knowledge on product development lifecycle Testing methodology and standards (Water Fall/ Agile) Knowledge in Test Automation scripting languages (e.g. Python Perl TCL) Knowledge with Wired (USB Ethernet PLC SCADA etherCAT Modbus RSxxx & Wireless technologies like NFC Bluetooth Wi-fi Zigbee etc. is a plus Understanding of automation frameworks (e.g. Hudson/Jenkin) Knowledge and knowhow on Diesel and Gasoline Engine Management Systems Knowledge of embedded algorithm integration on platform (Windows Linux and Android) Comprehension of ASPICE & ISO26262 process Knowledge in Pre-Silicon Verification environments for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge of MISRA 2004 and 2012 Coding guidelines (PC-lint LDRA & PRQA) Knowledge of CAN Tools: CANoe CANalyser & CAPL programming Knowledge of GDT framework internals Additional Comments Microcontroller ( STM32) Communication Protocols :- SPI, QSPI, I2C, UART, MODBUS Languages: C, C++, Java, Python Other:- Timer, PWM, Ethernet, RTC, TCP/IP. OS: Linux Proven experience in embedded firmware development, specifically with STM32 microcontrollers. Perform code reviews and maintain documentation for firmware development processes. Proficient in C/C++ programming languages. Experience with development tools such as STM32CubeIDE, IAR Embedded Workbench, or Keil. Experience with communication protocols (SPI, I2C, UART, Modbus etc.). Experience with Timer, PWM,ADC, QSPI, Flash, EEPROM, Uart RS285, Secure element, Ethernet. Experience in HMI interface. Experience in CyberSecurity, Mbedtls. Experience with real-time operating systems (RTOS) . Skills Microcontrollers,Spi,Embedded Show more Show less

Job description: Job Description The ASIC Front-End Head is responsible for leading the front-end design team, ensuring high-quality Application-Specific Integrated Circuit (ASIC) designs, and driving innovation in digital chip development. This role requires expertise in RTL design, verification, synthesis, and architecture development, along with strong leadership and strategic planning skills. Key Responsibilities • Technical Leadership: Define and implement best practices for front-end ASIC design, ensuring efficiency and performance. • Architecture & Design: Oversee the development of digital circuits, including RTL coding, synthesis, and timing analysis. • Verification & Validation: Ensure robust design verification methodologies using tools like UVM, SystemVerilog, and simulation frameworks. • Cross-Team Collaboration: Work closely with back-end design, physical design, and fabrication teams to optimize chip performance. • Innovation & R&D: Stay updated with emerging semiconductor technologies and drive research initiatives. • Mentorship & Team Development: Guide and mentor engineers, fostering a culture of learning and technical excellence. • Technical Project Management: Oversee front-end development timelines, ensuring timely delivery of high-quality designs. Required Qualifications • Education: Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a related field. • Experience: 15+ years in ASIC front-end design, with a proven track record of successful projects. • Technical Skills: Expertise in HDLs (Verilog, VHDL), synthesis tools, timing analysis, and low-power design techniques. • Leadership & Communication: Ability to lead teams, manage projects, and communicate effectively with stakeholders. • Problem-Solving: Analytical mindset with a passion for optimizing digital designs for performance and efficiency. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER The Role The focus of this role is to plan, build, and execute the Power analysis and optimization of new and existing features for AMD’s APU, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: required to be experienced in power estimation, analysis, optimization experience with tools PTPX/Power Artist physical design experience with ICC/Innovus, and saif based power optimization is a plus front end design knowledge data paths understanding, reviewing waveforms etc,. is a plus knowledge of power management methodologies (including clock gating, power gating, voltage frequency scaling, etc...) is a plus Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ LEAD VERIFICATION ENGINEER The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements Preferred Experience Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts - Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge. Experience in Power Management and Power aware UPF based verification Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. Academic Credentials Bachelors or Masters degree in computer engineering/Electronics/Electrical Engineering Experience :7-12 Years Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Hiring Remote Frontend Developers | Earn ₹ 1,30,000/Month About the Role: We're hiring a Frontend Developers to join our growing team of passionate technologists. This is an ideal role for early-career developers seeking to gain real-world experience , contribute to live projects, and grow under the guidance of experienced engineers, all while working remotely. Whether you're a recent graduate, self-taught programmer, or switching into tech, this role allows you to build your skills in a real development environment , on a flexible schedule that fits your lifestyle. What You'll Do: Work on real coding projects in collaboration with cross-functional remote teams Write, test, and debug code in modern programming languages like JavaScript, Python, or Java Learn version control (Git), issue tracking, and agile workflows Participate in virtual meetings, peer code reviews, and guided mentorship sessions Contribute to web or software development projects and gain experience across front-end and back-end systems Receive structured feedback and continuous learning support What Were You Looking For: Proficiency in at least one of the following programming languages: Java / Python / JavaScript / TypeScript / C++ / Swift / Verilog. Must have an educational background in Computer Science Basic familiarity with version control (Git), databases, or web development is a plus Strong desire to learn and grow in a remote tech environment Ability to communicate clearly and collaborate asynchronously A proactive mindset and consistent access to a computer and stable internet Compensation & Benefits Earn ₹1,30,000/month. Flexible remote work schedule (5–10 hours/week). Free access to advanced AI tools and platforms. 🌍 Why Join Us? Be part of a global network of coding experts advancing AI with flexibility, transparency, and cutting-edge resources. Show more Show less

Grow with us About this opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Primary country and city: India (IN) || Bangalore Req ID: 768495

AECG ASIC DFx - MTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .