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Digital Verification Engineer - UVM/System Verilog

5 - 10 years

6 - 10 Lacs

Posted:7 hours ago| Platform: Naukri logo

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Work Mode

Remote

Job Type

Full Time

Job Description

- Expertise in the verification of IP or SOC cores. - Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage. - Experience in CXL / DDR / MIPI / PCIe Protocol - Understanding of BIST would be an added advantage. - Familiarity with HDL's such as Verilog and scripting languages such as shell/Perl/Python etc.is highly desirable - Good communication skills, debug and problem solving skills. - Be a technical contributor in the Verification Tasks - System Verilog/Verilog coding of test benches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM. - Work closely with team members to deliver quality products. - Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs - Works in a project and team oriented environment - Preferred GCC / USC or candidates with valid H1B

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