640 Semiconductor Jobs - Page 5

About Marvell . Your Team, Your Impact The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications. What You Can Expect Develop the architecture for a functional verification environment, including reference models, bus-functional monitors, and drivers Contribute to the development methodology and extend RoCE-related learnings within the team Write comprehensive verification test plans using random techniques and coverage analysis, in collaboration with design teams Develop test cases and tune the environment to meet coverage goals; debug failures and work with designers to resolve issues Verify boot code and architect, develop, and maintain tools to streamline the design of advanced multi-core SoCs Translate engineering requirements into scalable and user-friendly software tools optimized for highly parallel compute environments Perform unit and regression testing of developed software tools What Were Looking For BS in Computer Engineering, Electrical Engineering, or Computer Science with 15+ years of verification or design experience, or MS/PhD with 10+ years of experience Hands-on expertise in RoCE (RDMA over Converged Ethernet) Strong experience with SystemVerilog and UVM Proven ability to write detailed test plans and develop sophisticated directed and random verification environments Proficiency in scripting languages such as Python or Perl, and familiarity with EDA verification tools Experience with object-oriented design and implementation Good understanding of Linux operating systems Solid programming skills, especially in C++ and ARM assembly Working knowledge of high-speed Ethernet Understanding of other networking protocols is a plus Diligent, detail-oriented, and proactive, with the ability to manage tasks independently Open to feedback and able to work with diverse perspectives Flexible and adaptable; quick to learn in a fast-paced environment Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-KP1

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industrys most complex semiconductor chips. What youll be doing: As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression. Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features. In addition, you will help develop and deploy DFT methodologies for our next generation products. Be apart of innovation to strive improve the quality of DFT methods. You will also need to work with multi-functional teams to incorporate DFT features into the chip. Occasional travel and also some late hours online meetings involved during critical milestones. What we need to see: BSEE or MSEE from reputed institutions or equivalent experience. 2+ Years of experience preferably in Design for testability (DFT) You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design. Experience in RTL and Gates verification and simulation. You need to be familiar with BIST architecture and JTAG/IEEE1149. 1/IEEE1500. Strong DFT knowledge in Scan ATPG, compression techniques and memory test. Strong analytical and problem solving skills. Expert coding skills in industry standard scripting languages. Extraordinary written and oral communication skills with the curiosity to work on rare challenges. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If youre creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. #LI-Hybrid

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . The Principal Engineer - QMS / ASPICE Competent Assessor plays a critical dual-role in maintaining and improving the organizations Quality Management System while leading Automotive SPICE (ASPICE) assessment and compliance activities. This position consults on quality processes, supports internal and external ASPICE assessments, and drives process excellence across engineering projects. The ideal candidate will bring deep knowledge of quality standards, regulatory compliance, and hands-on experience in the automotive industry. Key Responsibilities: QMS Responsibilities: Lead the implementation, maintenance, and continuous improvement of the QMS in alignment with ISO standards in accordance with ADI Central Quality (e.g., ISO 9001, IATF 16949). Oversee and support CAPA, internal audits, document control, and process improvements. Provide subject matter expertise on regulatory and customer-specific requirements across functions. Train and mentor BMS teams on QMS procedures, quality tools, and compliance expectations. Analyze quality metrics and use data-driven methods to identify trends and implement corrective actions. Ensure audit readiness and support internal and external QMS audits. ASPICE Assessor Responsibilities: Drive the design, implementation, and maintenance of processes and documentation. Act as a subject matter expert (SME) for regulatory and quality standards applicable to the Automotive business. Plan, perform, and support Automotive SPICE (ASPICE) assessments (Gap, Project, Internal). Define, implement, and maintain the internal ASPICE assessment standard. Deliver overview and detailed ASPICE training courses; continuously enhance training content. Analyze assessment findings and support development of improvement plans including identification, prioritization, and verification of actions. Consult internal teams and customer-facing projects on ASPICE compliance, process tailoring, and implementation. Support embedding ASPICE requirements into the organizations QMS and engineering processes. Collaborate with Engineering Quality to ensure alignment between QMS, ASPICE, and project execution. Support and lead external audits/assessments, including but not limited to ASPICE, ISO26262, ISO21434 and ISO9001 audits; ensure audit readiness across BMS. Provide quality engineering support for running and upcoming projects including product development, process improvement, and change control. Train and mentor project/product teams on processes and regulatory requirements. Drive harmonization and standardization efforts across multiple locations and business units, if applicable. Ensure robust document control and record management systems are in place and maintained. Stay current with evolving regulations and industry standards; interpret and communicate their impact to stakeholders. Qualifications: Bachelor s or Master s degree in Engineering, Quality, Life Sciences, or related field. Minimum of 10+ years in quality systems and/or regulatory roles, with at least 3 years in a senior engineering capacity. In-depth knowledge of Quality and QMS standards along with regulations (e.g ISO 9001, ISO 26262, ASPICE, UNECE, ISO 21434 etc.). Experience in a regulated industry such as Automotive, Rail, or high-tech manufacturing. Strong understanding of risk management, CAPA and root cause analysis. Certification(s) in atleast one or more areas as ASPICE, AgileASPICE, ASPICE CS, ISO26262, ISO21434 CACSP, CQE, CQA, or Six Sigma is highly desirable. Excellent project management, conflict management, communication, and problem-solving skills. Familiarity with embedded development and automotive software/system development lifecycles. Advanced knowledge of quality tools and techniques (e.g., 8D, Ishikawa, FMEA, Peer Reviews). Proven experience conducting ASPICE assessments, process gap analyses, and improvement planning.Bottom of Form

As we continue to grow and expand our product offerings, a automation engineer helps us to maintain the quality and reliability of our software applications. We are looking for Test Automation Engineer with experience in testing web application and APIs using Python/Typescript and technologies such as Playwright, Pytest or Jmeter to ensure the success of our software development projects. Job Description In your new role you will: Develop test strategies, automation framework and plans in accordance with epic/user stories/biz requirements and ongoing learnings. Define test metrics, execution plan, create and maintain test cases and automate them using identified framework. Analyzing and reporting test results to identify areas of improvement. Focus on quality, continuous improvement of tests and test efficiency. Drive towards frequent regression testing, maintain CI/CD infrastructure, test base, test execution, resolution measures. Modernizing existing test automation setup Participating in Agile development, testing and releases, including sprint planning and retrospectives Ability to create Dashboards in Tableau, ELK dashboard or any out of the test results. Your Profile You are best equipped for this task if you have: Bachelors degree in Computer Science/Information Technology or equivalent. 3+ years of experience in Web based tools/applications test automation and development. Programming skills in Python and Test automation for RestAPI, WebUI and Load testing . Hands on experience in test frameworks like Winium, Selenium, JUnit, NUnit, PyTest along with Jenkins / GIT / Bitbucket / Gitlab / Jira . Hands on experience in performance testing JMeter, LoadRunner or Gatling . #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone.

Were seeking a skilled Software Validation Verification Engineer to join our team, responsible for ensuring the quality and reliability of our software products. As a key member of our Software Validation Verification team, you will design, implement, and execute comprehensive test plans and test cases using a combination of automation and manual testing techniques for cloud based solutions. Job Description In your new role you will: Design, implement and execute test plans and test cases. Develop and maintain automated test frameworks. Identify, document, and track software and system defects. Continuously review and improve quality assurance processes. Collaborate with development teams to ensure product quality. Your Profile You are best equipped for this task if you have: 9 to 12 years experience in testing of IoT Products and Solutions. Experience with Restful API testing (postman tool). Experience in AWS API test automation with Postman . Experience and hands-on experience with CI/CD tools (preferably Gitlab) Hands-on Experience with Python for simulator device testing. Demonstrate experience in developing end-to-end automation scripts with test tools - K6 and JMeter . Strong problem-solving skills; adaptable, proactive, and willing to take ownership. Experience in common source code control systems (e. g. git). Experience in writing clear, concise, and comprehensive test plans and test cases. Experience understanding customer requirements to develop testing approaches for improving usability, functionality, and consistency with a focus on the end-user experience. Hands-on experience with both white box and black box testing. Hands-on experience with automated testing tools. Experience working in an Agile/Scrum development process. Good to have Docker Containers understanding. Experience in AWZ services , especially IOT core, S3, SNS, device management, lambda, cloud watch is an added advantage. #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone.

We are looking for Test Automation Engineer with experience in testing web application and APIs using Python/Typescript and technologies such as Playwright, Pytest or Jmeter to ensure the success of our software development projects. As we continue to grow and expand our product offerings, we need experienced automation engineers who can help us maintain the quality and reliability of our software applications. Job Description In your new role you will: Develop test strategies, automation framework and plans in accordance with epic/user stories/biz requirements and ongoing learnings. Define test metrics, execution plan, create and maintain test cases and automate them using identified framework. Analyzing and reporting test results to identify areas of improvement. Focus on quality, continuous improvement of tests and test efficiency. Drive towards frequent regression testing, maintain CI/CD infrastructure, test base, test execution, resolution measures. Modernizing existing test automation setup. Participating in Agile development, testing and releases, including sprint planning and retrospectives. Ability to create Dashboards in Tableau, ELK dashboard or any out of the test results. Your Profile You are best equipped for this task if you have: Bachelors degree in Computer Science/Information Technology or equivalent. 5+ years of experience in Web based tools/applications test automation and development. Programming skills in Python and Test automation for RestAPI, WebUI and Load testing . Hands on experience in test frameworks like Winium, Selenium, JUnit, NUnit, PyTest along with Jenkins/ GIT/ Bitbucket/ Gitlab/ Jira . Hands on experience in performance testing like J Meter, LoadRunner or Gatling . #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone.

The Impact You ll Make As a Sr. Group Manager, Program Management at Lam, you will play a pivotal role in developing India Supply Chain ecosystem as part of a key strategic supply chain initiative for the organisation. You ll be at the forefront of project initiation through delivery, using your expertise to coordinate cross-functional teams and ensure project are completed on time and within budget. What You ll Do Sr. Group Manager, Program Management manages the Strategic initiative of India Supply Chain ecosystem development through an effective Cross Functional engagement of Commodity Team, Product Group Engineering and other functions within Global Operations. As a Senior Staff of the Supply Chain Leadership team, the primary role is to create the strategic roadmap Year on Year and hold the teams accountable through effective progress check and meeting milestones defined as part of the strategic program. Accountable for establishing visible impact of meeting the objectives around Supplier Selection, Qualification of parts in time and meeting the supply chain performance metrics such as cost, quality, capacity, and on-time delivery requirements of Lam Research products. Program Management across all the commodities identified for the India Sourcing program. Program review updates to Senior Executive leadership to identify and mobilize the support required. Acts as a point of contact for all escalations from Product group to Supply Chain, liaison between Engineering Product management and Supply Chain functional organization Provide actionable insights for management to influence decision making through data collection and analysis. Develop and deliver clear and concise communications for leadership teams and stakeholders. Ensure execution, manage risks, assure adherence to program or project schedules, and performance to meet business requirements. Works in a cross-functional team environment within a matrix organization with internal customers, including high-level executives, to regularly monitor the progress. Define and monitor metrics in line with AOP (annual operating plan) objectives relative to supplier performance against these expectations to ensure continuous supplier improvement; then drives team to address and close gaps to meet objectives This role will also require flawless delivery of activities resulting in the highest level of product and service quality as viewed through the eyes of Lam s customers. Who We re Looking For Minimum Qualifications: Bachelor s degree in Supply Chain, Operations Management, Business, Engineering, or related field with 15+ years of experience; or Master s degree with 14+ years experience; or equivalent experience. 12+ years of related experience in project management or program management Experience leading cross-functional teams and influencing stakeholders. Advanced analytical skills to interpret and utilize data for decision support. Proven ability to gain partnerships and in a cross-functional environment with Sourcing, Engineering, manufacturing, quality as well as procurement, finance, and product support. Prior experience in managing multi-disciplinary teams of Supply Chain Sourcing and other process Knowledge of manufacturing methods and supply chain knowledge in commodity sourcing Additional required skills include leadership skills, strategic thinking, attention to detail for everyday tactical execution, and excellent people management Demonstrated skill in decision making and problem solving and experience in making business judgments Demonstrated experience in strategic planning - setting vision and objectives, creating strategies, forecasting, and budgeting Demonstrated experience in talent and organization development Proficient in Data Analytics Presentation Skills Familiar with and uses Quality Principles such as Lean, Six-Sigma, etc Preferred Qualifications Program Management / Commodity Management / Supply Chain Leadership in large manufacturing operations groups for MNC product-based company. Familiarity with semiconductor, Electrical equipment Manufacturing or high-technology supply management practices, standards, and organizations. Experience in Global Sourcing / Localization Our Commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Companys intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories - On-site Flex and Virtual Flex. On-site Flex you ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. Virtual Flex you ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Job Responsibilities Translate the design specification to an optimal micro-architecture for digital blocks RTL coding using Verilog and System Verilog Meet power, performance and area goals by micro-architecture optimization Block level Designer verification Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Work closely with DFT and PD teams for signoff Support Silicon validation Position requirements BE/BS/Mtech/M.E/PhD degree in Electrical/Electronics/Computer science from a reputed institute 3-10 years of relevant experience Digital logic design and hands-on RTL coding experience, simulation, debug Experience in writing and debugging timing constraints at block and full-chip level Experience in Synthesis and LEC Good verbal and written communication skills to work effectively with teams spread geographically Experience in digital signal processing and Matlab modeling is highly desirable Experience in Processor subsystem design /SOC is a plus

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Job Responsibilities Implementing RTL to GDS2 flow Floor-planning, Placement, CTS, Routing using physical design tools Synthesis, LEC Debugging timing constraints , Static timing analysis as part of Physical Design flow Extraction, Physical Verification(LVS/DRC) Crosstalk analysis, EM/IR analysis Position requirements BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute 2-6 years of relevant experience Hands on experience doing physical design and timing closure of complex blocks Strong understanding of timing, power and area trade-offs and optimization of PPA Knowledge of clock tree synthesis optimization to meet latency, skew goals Understanding timing Constraints and debugging through PD flow Knowledge of Design Margins timing corners, Timing analysis and signoff timing closure Good Debugging skills in resolving Congestion and Timing, SI/CrossTalk Analysis and Write Timing/Functional ECOs Exposure in signoff Power, IR and Physical Verification at both block and chip level is desirable Experience with scripting and automation - Perl/Tcl/shell and implementation flows Good verbal and written communication skills to work effectively with teams spread geographically

Interested to make a difference and provide tech leadership! Hands on expeirence of Software develoment skills along with Devops experience for global delivery then apply now. In your new role you will: Development of Python automation for GitLab CI Pipelines. Development of Docker containers in support of the Pipelines. Integration of IT-provided services such as BlackDuck, Coverity. Integration of Modus ToolBox software assets into CI/CD release pipeline . Liaise with asset development teams on infrastructure, toolchain and CI/CD release pipeline. Liaise with IT on operations support You are best equipped for this task if you have: Minimum bachelor in computer science or software engineering. Master degree preferred. 10 years work experience Skilled in software engineering with good knowledge of software development, DevOps, pipelining, containerization and micro-service deployments. This position will represent DevOps in Bangalore and will therefore liaise with leadership/developers in that design center. High communication skills needed and the ability to work independently given the functionalmanager is in the United States. #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone.

Mesh / Coherency Design Verification Engineer in Pune, MH, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Mesh / Coherency Design Verification Engineer in Pune, MH, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Mesh / Coherency Design Verification Engineer in Bangalore, KA, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Mesh / Coherency Design Verification Engineer in Bangalore, KA, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

At SolarEdge (NASDAQ: SEDG), were a global leader in smart energy technology, with over 4,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. Were committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry thats always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. Our RD division is growing globally, and we are looking for an experienced Senior Power Electronics Engineer to join our dynamic team at the new RD site in Bangalore, India. As a Senior Power Electronics Engineer at SolarEdge India RD , you will play a pivotal role in the design, development, and optimization of power electronics and power electronics systems for our advanced solar energy products. You will be responsible for driving the innovation and technical excellence of our power solutions, contributing to the success of SolarEdges mission to make solar energy more accessible and efficient. Responsibilities: Lead the design, analysis, and development of advanced power electronics and power systems for SolarEdges solar energy products, including inverters, power optimizers, and energy storage solutions. Collaborate with cross-functional teams, including electrical engineers, Mechanical Engineers/Designers, PCB Layout Engineers, and firmware developers, to ensure seamless development, integration, and optimization of power systems. Conduct power system studies, such as load flow analysis, transient stability, and harmonic analysis, to assess system performance and reliability. Perform detailed design and analysis of power electronic circuits, ensuring compliance with industry standards and safety regulations. Prepare detailed design documentation, Schematics, BoM, and test procedures. Lead the testing and verification of power electronics and power systems, both in the lab and field, to ensure they meet design specifications and quality standards. Participate in design reviews, providing technical expertise and guidance to the team to drive continuous improvement and innovation. Collaborate with suppliers and manufacturing teams to support the transition of designs from RD to mass production, addressing any design-related issues during production. Mentor and guide junior engineers, fostering a collaborative and innovative work environment. Bachelors (B.E./B.Tech.) in Electrical/Electronics Engineering with 8+ years of relevant industrial in power converter design and development ( Or ) Master s degree (M.E./M.Tech) in Electrical/Power Electronics/Energy System Engineering with 6+ years of relevant industrial experience in power electronics design and development ( Or ) Ph.D . in Electrical / Power Electronics with 3+ years of relevant industrial experience in power electronics system analysis and design, preferably in the solar energy or renewable energy industry. Experience with simulation tools (e.g., PLECS, PSpice, LT SPICE, Simulink etc.) Knowledge of power converter topologies (e.g., DC/DC, DC/AC and AC/DC ), including resonant and bi-directional converters and grid-tied inverters . Strong understanding of Power Semiconductor devices (Including SiC and GaN ), gate drive circuits , and magnetic components used in power converters. Excellent knowledge of PCB layout rules , considering high-current traces, thermal management, creepage, clearance requirements for HV and LV traces. Ensure compliance with best practices for power distribution, component placement, and impedance control. Implement EMI/EMC best design practices to ensure compliance with regulatory standards. Familiarity with international safety and regulatory standards for power electronics and solar energy products. SolarEdge is committed to seeking out and retaining the finest human talent to ensure top business growth and performance.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Senior Digital Design Engineer - PCIe We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities: Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPs and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows Basic Qualifications / Experience Level: Bachelor s in Electronics/Electrical engineering (Masters preferred). 8+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise: Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes ( Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles . Hands-on experience with processor IP (ARM/ARC) Experience of working on PCIe is a must. Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Hands-on experience with complex DMA engines and FW interaction. Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Experience with block-level and full-chip design at advanced nodes ( 16nm). Silicon bring-up and post-silicon debug experience. Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Preferred Experience: Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus. Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience of working on PCIe/UAL is a big plus. Understanding of PAD design, DFT, and floor planning. Experience in synthesis, and timing closure is a big plus. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Summary: As a Static Timing Analysis (STA) Engineer at Astera Labs, you will play a pivotal role in ensuring our digital ASIC designs meet stringent timing and performance requirements, with a strong emphasis on Design for Test (DFT). You will be responsible for timing analysis, identifying critical paths, and driving timing closure across complex ASICs and chiplets. This is a unique opportunity to contribute to the development of cutting-edge silicon for AI infrastructure. Key Responsibilities: Collaborate with design and architecture teams to define and refine timing constraints for DFT across complex ASICs and chiplets. Perform timing analysis and signoff in all DFT modes using industry-standard tools such as PrimeTime. Analyze and resolve timing violations, with a focus on test modes and scan paths. Integrate and validate timing constraints from third-party IPs and external vendors. Generate detailed timing reports, highlighting violations and providing optimization recommendations. Work closely with RTL, physical design, DFT, and verification teams to resolve timing-related issues. Contribute to the development and enhancement of STA methodologies, flows, and automation. Demonstrate a professional attitude with the ability to prioritize tasks, plan effectively for meetings, and work independently with minimal supervision. Exhibit an entrepreneurial mindset and a can-do attitude, acting quickly and decisively with the customer in mind. Collaborate effectively with cross-functional and globally distributed teams. Basic Qualifications: Bachelor s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master s degree with 6+ years. Proven experience with block- and full-chip timing constraints, including test modes. Strong understanding of DFT architectures and hands-on experience closing timing specifically for DFT. Experience integrating third-party IPs and managing associated timing constraints. Proficiency in STA tools such as PrimeTime and scripting for automation. Preferred Qualifications: Experience with automated constraint generation and validation tools. Familiarity with high-speed interfaces such as PCIe, CXL, and DDR. Strong communication and collaboration skills in cross-functional, globally distributed teams. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Marvell . Your Team, Your Impact Central Engineering (CCDS) - ASIC India in Marvell is a Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements. What You Can Expect The candidate Marvell is looking for will have: Very good knowledge on SCAN/ATPG/JTAG/MBIST Good Knowledge and understanding on JTAG for IEEE1149. 1/6 standards Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools) Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques Proven experience in Scan insertion techniques at block level and Chip top level Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team Good knowledge on Perl/ Tcl scripting Proven experience on gate level simulations with notiming and SDF based simulations Experience with Post-Si ramp up and debug on ATE Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and at least 5 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-4 years of experience. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Work Schedule Standard (Mon-Fri) Environmental Conditions Office Job Description Thermo Fisher Scientific Inc. is the world leader in serving science, with an annual revenue of approximately $40 billion. Our Mission is to enable our customers to make the world healthier, cleaner and safer. Whether our customers are accelerating life sciences research, solving sophisticated analytical challenges, growing productivity in their laboratories, improving patient health through diagnostics or the development and manufacture of life-changing therapies, we are here to support them. Our distributed team of more than 130,000 colleagues delivers an unrivalled combination of innovative technologies, purchasing convenience and pharmaceutical services through our industry-leading brands, including Thermo Scientific, Applied Biosystems, Invitrogen, Fisher Scientific, Unity Lab Services, Patheon and PPD. For details, visit www.thermofisher.com We are looking for a strategic, technically strong, and people-oriented Senior Manager to own the development of software applications that powers our world-class electron microscope systems . This individual will play a key role in guiding software teams that enable scientific breakthroughs in materials science, life sciences, and semiconductor research. As a senior leader you will lead all aspects of software programs across AI platform, Test infrastructure, Cybersecurity and other teams collaborating with cross-disciplinary R&D teams. Key Responsibilities Lead and mentor a team of software engineers, test engineers, tech leads, across multiple projects. Build a motivating environment that champions innovation, ownership, and continuous learning. Conduct performance evaluations, career development planning, and skills growth initiatives. Own delivery of software features on time and within scope across multiple agile teams and release trains. Identify risks, drive resolution of technical blockers, and implement process improvements. Engage with senior leadership and external collaborators to align roadmap, priorities, and resourcing. Represent the software organization in program reviews, customer interactions, and technical deep dives. Champion software scalability, modularity, and maintainability to support next-gen microscopy systems. Qualifications: Bachelor s / Master s degree in computer science, Software Engineering, or related field 15+ years of experience in software engineering, with 5+ years in people or program leadership roles. Experience leading software development for complex instrumentation, ideally in scientific, medical device software products. Strong understanding of software development lifecycles, Agile/Scrum methodologies, and CI/CD practices Excellent leadership, communication, and stakeholder management skills Familiarity with software used in imaging, data acquisition, or scientific workflows Experience working in a global, matrixed R&D environment

Title: Memory IP Design Engineer- (eFuse) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Memory Design Engineer to work in the Memory IP group in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks like decoders, sense amplifiers, write drivers etc. Your Job: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IP s on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 4-20 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys ) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

Title: Senior Technical Writer Location: Bangalore, India Job Term: Full-Time Picarro is a leading technology company specializing in high-precision gas analyzers and optical spectroscopy instruments based on Cavity Ring-Down Spectroscopy (CRDS) for ultra-sensitive trace gas detection. We serve a diverse range of industries. In natural gas, we help optimize utility networks with advanced methane detection and real-time insights; in ethylene oxide compliance, we support sterilization facilities in meeting evolving regulations through reliable monitoring and expert guidance; in environmental science, we provide accurate, low-maintenance gas and isotope data for impactful research; and in the semiconductor industry, we deliver parts-per-trillion-level AMC monitoring to protect cleanrooms, improve yield, and reduce downtime. The Opportunity We re seeking an experienced and detail-oriented Senior Technical Writer / MadCap Flare Developer to join our team in India, supporting cutting-edge solutions in the emission monitoring industry. This is a unique opportunity for a seasoned professional who thrives on transforming complex technical information into clear, user-friendly content and brings deep expertise in MadCap Flare to design, manage, and optimize to build modern and scalable documentation systems. In this dual-capacity role, you will play a critical part in shaping the future of our product documentation, collaborating closely with engineering, product management, and product marketing teams to ensure our users receive accurate, engaging, accessible, and high-quality information. If youre passionate about technical communication and excited to lead innovation in content development tools and strategies, we want to hear from you. Key Responsibilities Create and Maintain Technical Documentation Develop clear, concise, and user-friendly documentation including user manuals, service guides, technical and reference materials for hardware and software products ensuring clarity, accuracy, and compliance with regulatory standards. Content Management and Tools Expertise Design and manage scalable, topic-based documentation projects using MadCap Flare, including multi-channel outputs (HTML5, PDF, Webhelp), content reuse strategies, and version-controlled workflows (e.g., Git, MadCap Central). Integrate Flare outputs with external systems such as CMSs, knowledge bases, or custom portals using RESTful APIs, and develop scripts or workflows for automated content delivery. Lead Cross-Functional Documentation Projects Collaborate with engineering, product management, regulatory, and support teams to gather technical information, clarify requirements, and drive documentation projects from planning through delivery, ensuring high-quality content is delivered on time and aligned with product releases. Implement Best Practices and Style Guides Customize and maintain MadCap Flare stylesheets, templates, and master pages to ensure brand consistency and a seamless user experience, while troubleshooting and resolving issues such as broken links, output errors, conditional text problems, and formatting inconsistencies. Support Localization Efforts Support in-house translation and localization processes by preparing source content, collaborating with internal language teams, and ensuring consistency across multilingual documentation. Develop Visual and Multimedia Content Create clear and visually effective technical illustrations and graphics using Adobe Creative Suite or equivalent tools to enhance understanding of complex processes or systems. Requirements Technical Skills: 3+ years of hands-on experience with MadCap Flare, including topic-based authoring, content reuse strategies, TOC and index creation, variables, and conditional tagging. Proficiency in creating and managing multi-channel outputs (HTML5, PDF, Webhelp, etc.). Strong understanding of CSS, HTML, and XML as they apply to Flare templates and outputs. Working knowledge of RESTful APIs and how to leverage them to automate publishing workflows, data exchange, or synchronization between Flare and other platforms. Strong problem-solving skills with the ability to troubleshoot and debug issues within MadCap Flare, including broken links, stylesheet conflicts, conditional text rendering, build errors, and output inconsistencies. Experience with source control systems such as MaCap Central, Git or equivalent for managing documentation projects. Ability to develop and maintain project templates, style sheets, and master pages to enforce branding and consistency. Knowledge of MadCap Central for content review, version control, and team collaboration (preferred). Familiarity with single-sourcing techniques and best practices for scalable content management. Documentation & Industry Expertise: Experience working with technical documentation in industrial domains, preferably in emission monitoring, environmental compliance, instrumentation, or related engineering fields. Ability to interpret complex technical specifications, engineering diagrams, and regulatory documentation to create clear and user-friendly manuals, guides, and help systems. Proficiency in creating clear and accurate technical illustrations using tools such as Adobe Illustrator, Photoshop, or other graphic design software, to visually support complex concepts, processes, or equipment used in emission monitoring systems. Experience with translation and localization workflows is a plus, including working with translation memory tools, preparing content for multilingual output, collaborating with internal language teams, and ensuring consistency and accuracy across localized documentation. Soft Skills: Excellent written and verbal communication skills in English. Strong attention to detail and commitment to documentation quality and accuracy. Proven ability to work independently and manage multiple documentation projects simultaneously. Comfortable collaborating with cross-functional teams including engineers, product managers, marketing, and QA experts. Education: Bachelor s degree in English, Technical Communication, Engineering, Computer Science, or a related field. MadCap certifications or relevant training (preferred but not mandatory). All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, national origin, protected veteran status, gender identity, social orientation, nor on the basis of disability. Posted positions are not open to third party recruiters/agencies and unsolicited resume submissions will be considered free referrals.

THE ROLE: Join AMD as we push the boundaries of whats possible in graphics and compute technology. We are seeking a talented RTL Physical Design Engineer to contribute to the development and optimization of our cutting-edge CDNA and RDNA graphics IP. This role involves transforming sophisticated RTL designs into robust and efficient physical layouts, critical to the performance of our next-generation graphics and compute solutions. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities: Physical Design Implementation: Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts. Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design thru mock-taepout Performance Optimization: Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products. Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives. Verification and Timing Closure: Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP. Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements. Collaboration and Communication: Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores. Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further. Documentation and Reporting: Maintain comprehensive design documentation, methodologies, and updates. Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered. PREFERRED EXPERIENCE: Domain Expertise: Experience with working on complex design and optimizing for performance, power, and area. Technical Proficiency: Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores. Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime. Experience with low-power design methodologies and techniques for high-performance graphics IP. Design and Verification: Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks. Strong skills in signal integrity analysis, including crosstalk and IR drop evaluations. Process Technology: Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below). Knowledge of process-related challenges and optimization techniques for graphics applications. Scripting and Automation: Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency. Experience developing and maintaining scripts for design rule checks and optimization processes. Problem-Solving and Innovation: Demonstrated ability to solve complex design challenges using innovative approaches. A track record of contributing to the improvement of design techniques and methodologies in a graphics-focused engineering team. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Participate in the development and testing of Field-Programmable Gate Arrays (FPGAs) for various projects. In your new role you will: Experience with FPGA design and development Proficiency in Vivado and other design software Providing Simulation of digital designs and design FPGA board Design emulation circuits for analog parts with discrete device Experience with lab equipment and testing procedures Validating on lab testing of FPGA Strong understanding of digital and analog circuit design Strong analytical and problem-solving skills You are best equipped for this task if you have: Master s or Bachelor s Degree in Electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in FPGA design, preferred with Xilinx/Vivado. Experience in digital and mixed-signal design, particularly with System Verilog. Good Analytical skills and good understanding of digital and mixed signal designs. Familiarity with power conversion topologies, such as DC/DC and AC/DC converters, is highly desirable. Experience in pre-silicon verification would be a plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Contact: Garima Chauhan - garima,chauhan@infineon.com We are on a journey to create the best Infineon for everyone.

Title: Memory IP Design Engineer- (eFuse) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Memory Design Engineer to work in the Memory IP group in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks like decoders, sense amplifiers, write drivers etc. Your Job: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IP s on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 4-20 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys ) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills.

The Group You ll Be A Part Of In the Global Products Group, we are dedicated to excellence in the design and engineering of Lams etch and deposition products. We drive innovation to ensure our cutting-edge solutions are helping to solve the biggest challenges in the semiconductor industry. The Impact You ll Make As a Project Engineer at Lam, youre not merely managing projects - youre driving advancements integral to the design and development of Lams products. Leading cross-functional teams, youll steer the execution of engineering projects, leveraging your technical prowess and strategic insight to deliver enhanced products. Your focus on continuous improvement in the development lifecycle will be pivotal as you own project to optimize and enhance Lams offerings. What You ll Do Who We re Looking For Minimum of 5 years of related experience with a Bachelor s degree; or 3 years and a Master s degree; or a PhD without experience; or equivalent work experience. Preferred Qualifications Our Commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Companys intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories - On-site Flex and Virtual Flex. On-site Flex you ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. Virtual Flex you ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.