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2.0 - 20.0 years

0 Lacs

noida, uttar pradesh

On-site

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System Verilog, UVM-based environments, AXI3/4/5, and preferably PCIe. Previous experience in RTL design of complex protocols and IP development teams is highly advantageous. As a member of the Cadence High-Speed SerDes PHY IP Front end Design team, you will be responsible for defining microarchitecture, leading ASIC design, collaborating with cross-functional teams, mentoring junior members, and fostering a high-performance team culture. Requirements for this role include a Bachelor's degree in Electronics Engineering with at least 7 years of experience, a Master's degree with 5 years, or a Ph.D. with 2 years in Digital Design. You should have hands-on experience in micro-architecting digital blocks, RTL implementation in Verilog/SV, SDC definition, STA, Lint Checks, CDC, and Synthesis. Knowledge of protocols such as Ethernet, USB, PCIe, MIPI(DPHY), and HDMI/Display is desired, along with the ability to work closely with Analog design teams and develop high-speed critical digital circuits and signal processing blocks.,

Posted 2 days ago

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3.0 - 7.0 years

0 Lacs

karnataka

On-site

The job requires a deep understanding of protocols such as USB, PCIE, MIPI, JEDEC, I2C, and SPI. You will be responsible for designing and verifying RTL code for high-speed SerDes digital blocks. Your communication skills, both verbal and written, should be excellent. Experience in synthesizing complex SoCs block/top level and writing timing constraints is necessary. You should also have experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints, as well as post-layout STA closure and timing ECOs. Previous work in technology nodes of 45nm and below is preferred. Your mandatory skills should include Timing Closure, STA, ECOs, Synthesis, and SDC. A qualification of BE/B.Tech in VLSI/ECE is required. You should have at least 3 years of experience in the verification of analog mixed signal blocks. Proficiency in tools such as Cadence AMS tools, Verilog, VerilogA, and VAMS languages is essential. For any career-related inquiries or applications, please reach out to hr@terminuscircuits.com.,

Posted 6 days ago

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10.0 - 14.0 years

0 Lacs

karnataka

On-site

Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. We are currently looking to hire Senior ASIC SOC RTL Design Leads with a minimum of 10 years of experience in the field. The preferred locations for this position are Visakhapatnam or Bangalore. The ideal candidate should possess a Bachelor's degree in Computer Science or Electrical/Electronics with a strong background in ASIC SOC RTL (Micro-architecture). Knowledge and experience in ARM Processor Integration, particularly M55, is highly desirable. In addition, the candidate should have a solid understanding of design concepts, ASIC flow, SDC, STA reports, CDC logic, and lint rules. Familiarity with AMBA buses and common processor architectures like ARM and RiscV is also required. Experience in FPGA design, including part selection, pin assignment, timing constraints, synthesis, and debugging, is a plus. Proficiency in relevant tools such as Socrates, Core Consultant, xcellium, vcs, and JTAG debugging tools like Coresight and Lauterbach is preferred. Knowledge of low power design techniques and UPF is an advantage. As an RTL Engineer, the candidate will be responsible for working on IP, Subsystem, or SoC-related tasks. Key responsibilities include collaborating with architects, pre- and post-silicon verification teams to meet project deadlines, and coordinating with customer leads to ensure timely deliverables. If you meet the above requirements and are interested in this opportunity, please share your updated resume with us at maruthiprasad.e@eximietas.design.,

Posted 1 week ago

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15.0 - 23.0 years

15 - 25 Lacs

Hyderabad, Bengaluru

Work from Office

Key Responsibilities: Define and lead the strategy for VLSI front-end design services Build and scale high-performing VLSI engineering teams (from 50 to 500+) Engage with customer design managers and secure design wins through deep technical collaboration Mentor and upskill engineering teams in line with evolving industry needs Ensure successful delivery of ASIC design and verification projects Develop innovative proposals and drive new project wins Collaborate with internal resourcing teams and external partners to fulfill staffing needs Represent VLSI practice in industry forums and events Must-Have Skills: Strong leadership experience in VLSI/ASIC front-end engineering Expertise in RTL design, UVM-based verification, UPF/SDC, formal verification, emulation Hands-on with commercial EDA tools (Synopsys, Cadence, Siemens) Familiarity with Verilog and standard formats (LEF/DEF/SPEF) Client engagement, delivery management, and proposal leadership Good-to-Have Skills: Industry connects with EDA vendors, foundries, and Tier-1 semiconductor companies Knowledge of ASIC-package co-design Experience in defining VLSI roadmaps, SoW/MSA processes Automation exposure (Python/Perl) Awareness of semiconductor industry trends and competitor insights

Posted 3 weeks ago

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10.0 - 14.0 years

10 - 14 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Collaborate with customers to ensure Synopsys SDC Constraints solutions meet expectations and use cases Develop and integrate design methodologies with broader Synopsys toolsets Track customer engagements, priorities, and communicate effectively with Marketing and Upper Management Prepare and deliver technical presentations and training to customers and Field Application Engineers (FAEs) Routinely gather customer feedback to influence internal product roadmap and R&D prioritization Provide technical direction to R&D and champion critical customer-driven enhancements The Impact You Will Have: Increase customer satisfaction through tailored SDC solutions Strengthen product integration and ecosystem value of Synopsys offerings Enable more efficient internal and external communication with clear tracking and reporting Empower customers and FAEs via expert training and detailed documentation Directly shape product development and innovation through real-world customer insights Drive continuous improvement of front-end design flows and SDC methodology What You'll Need: BS in Electrical or Computer Engineering with 10+ years of experience in STA, synthesis, or front-end flows Strong experience with STA and SDC constraint development Proficiency with RTL, System Verilog, and scripting languages (Perl, Tcl, Python) Prior experience with logic synthesis tools and front-end methodologies Experience with SDC tools and RTL simulation/SVA is a plus Excellent communication and documentation skills to represent technical and customer needs effectively

Posted 1 month ago

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3.0 - 8.0 years

6 - 16 Lacs

Bengaluru

Remote

- Experience with SDC assembly - violations from timing reports and develop strategies for improvement [Tools] PrimeTime @ Synopsys - Tempus @ Cadence [Good to have] - Able to understand DC and AC characteristics listed in device datasheets

Posted 1 month ago

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4.0 - 9.0 years

4 - 9 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Desired Skills and Experience: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl or Python scripting skills. Prior experience with logic synthesis tools is required. Prior experience using or supporting SDC tools would be a significant plus. Prior experience with RTL simulation, SVA would be a plus. Prior experience supporting front-end EDA tools would be a plus. Sound communication skills, verbal and written. Ability to produce product requirement documents. BS EE/CE. 4 years experience with STA/Synthesis.

Posted 2 months ago

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10.0 - 15.0 years

5 - 7 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

What You ll Need: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl, or Python scripting skills. Prior experience with logic synthesis tools. Prior experience using or supporting SDC tools (a significant plus). Prior experience with RTL simulation and SVA (a plus). Sound communication skills, both verbal and written. Ability to produce detailed product requirement documents. BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows.

Posted 2 months ago

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7.0 - 12.0 years

35 - 65 Lacs

Hyderabad, Bengaluru

Work from Office

Greetings from Quest Global Please find the details and kindly send me your Profile . RTL Design 10-15 Years Location : Bangalore/Hyderabad 1. Should have worked on ASIC/SOC projects using 22nm or smaller technology node 2. Expertise in automated RTL Integration using any of the industry standard tool/EDA flow 3. Expertise in SDC and UPF constraints development and checking 4. Expertise in Timing violation debug/fix at netlist level 5. Good knowledge on AHB/AXI/APB/PIPE interface 6. Expertise in Lint, CDC and VCLP, Synthesis, LEC 7. Very Strong in Python and TCL scripting • Nice to have skills: 8. Exposure to PCIe/Ucie 9. Experience in Leading small rtl design team • Location: Bangalore and Hyderabad • Notice period: max 45 days Please forward your updated profile to chakradhar.marupuru@quest-global.com below details Current CTC : Expected CTC: Notice Period : Best Regards Chakradhar M , Email:chakradhar.marupuru@quest-global.com | www.quest-global.com. Assistant Manager Quest Global Whatsapp No : 99869 21214 , Mob: +601 736 16576 Quest Global, Penang – Mayang. Unit 1.13-17 GBS@Mayang , Lengkok Mayang Pasir, Bayan Baru 11950,Penang, Malaysia

Posted 2 months ago

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