Member Technical Staff SerDes Design and Verification

The job requires a deep understanding of protocols such as USB, PCIE, MIPI, JEDEC, I2C, and SPI. You will be responsible for designing and verifying RTL code for high-speed SerDes digital blocks. Your communication skills, both verbal and written, should be excellent. Experience in synthesizing complex SoCs block/top level and writing timing constraints is necessary. You should also have experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints, as well as post-layout STA closure and timing ECOs. Previous work in technology nodes of 45nm and below is preferred. Your mandatory skills should include Timing Closure, STA, ECOs, Synthesis, and SDC. A qualification of BE/B.Tech in VLSI/ECE is required. You should have at least 3 years of experience in the verification of analog mixed signal blocks. Proficiency in tools such as Cadence AMS tools, Verilog, VerilogA, and VAMS languages is essential. For any career-related inquiries or applications, please reach out to hr@terminuscircuits.com.,