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Principal Design Verification Engineer

Principal Design Verification Engineer

Mips

15 - 18 years

20 - 25 Lacs

Bengaluru

Posted:11 hours ago| Platform:

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Skills Required

soc verification c++ ace prototyping soc design verification test cases scripting axi fpga rtl coding shell scripting ahb perl system verilog tcl ocp architecture python cache asic verification c chi engineering rtl uvm verilog electricals

Work Mode

Work from Office

Job Type

Full Time

Job Description

Principal Design Verification Engineer

Job Overview

MIPS is seeking a highly experienced Senior Staff Design Verification Engineer with over 15 years of industry experience to lead verification efforts focused specifically on Coherency Manager and Cache Controller components. The successful candidate will have extensive hands-on experience utilizing advanced verification methodologies, including constrained random testing, formal verification, and coverage-driven verification. This senior role involves close collaboration with CPU architects, designers, and cross-functional global teams to ensure high-quality, high-performance processor designs.

Key Responsibilities

Lead and drive verification activities for Coherency Manager and Cache Controller IP to closure.
Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications.
Develop comprehensive verification plans and execute these plans through testbench creation, test case development, and rigorous analysis.
Create directed and constrained random test cases in SystemVerilog, Assembly, and C to verify complex coherency and cache management behaviors.
Employ formal verification techniques to augment random verification and ensure exhaustive coverage.
Analyze verification coverage metrics to identify and close coverage gaps efficiently.
Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell.
Mentor junior verification engineers, providing technical guidance and leadership within the verification team.

Qualifications

Master`s degree or higher in Electronics, Electrical, Computer Engineering.
15+ years of relevant verification experience, specifically in CPU or complex SoC verification.
Proven expertise in verification of Multicore and Multicluster Coherency, Cache Controllers, or similar blocks.
Deep knowledge and practical experience with verification methodologies such as UVM, constrained random, and formal verification.
Proficiency in SystemVerilog, Verilog, C, C++, and Assembly.
Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI.
Strong scripting skills in Python, Perl, TCL, or Shell.
Experience with CPU architectures, particularly RISC-V, ARM, or MIPS.

Preferred Experience

Experience with RISC-V architecture.
Familiarity with functional safety standards (e.g., ISO 26262).
Prior exposure to FPGA prototyping and emulation platforms.

What MIPS Offers

Opportunity to be part of a dynamic team creating industry-leading RISC-V processors.
Autonomy with extensive support from industry experts.
Opportunities for significant career growth and technical advancement.
Competitive compensation and comprehensive benefits package

About MIPS

MIPS is a pioneer in RISC-based computing with a legacy of innovation in high-performance microprocessor design. Today, MIPS continues this legacy by leading the adoption and advancement of the RISC-V architecture, delivering scalable processor solutions for cutting-edge computing applications.

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Principal Design Verification Engineer