411 Placement Jobs - Page 12

Role & Responsibilities: Establish and maintain strong relationships with aviation/aerospace/aeronautical/defence industry recruiters to facilitate placements for our students in technical roles, aligning with students' career interests. Guide students through the job search process, offering assistance with resume writing, interview techniques, and job referrals. Schedule and follow up on student interviews with potential employers. Stay updated on job opportunities by maintaining connections with professionals from various airlines and aviation companies. Provide counseling, career guidance, and skill enhancement to improve students employability. Organize guest lectures, training programs, and internships to further student development and industry readiness. Develop and execute comprehensive placement strategies to meet institutional and student goals. Conduct recruitment surveys and gather feedback to improve placement processes. Coordinate all placement-related activities and maintain a resume bank of students. Interact with previous recruiters to explore repeat placement opportunities. Attend seminars and training sessions to enhance professional development and industry knowledge. Perform additional duties related to placement as required. Exhibit excellent communication skills and a professional demeanor.

Role & responsibilities - Candidate should have good connect with the aviation industry recruiters to place our college students in both technical and non-technical field, such as cabin crew, ground staffing, hospitality, aircraft maintenance engineers, & aerospace engg, that match their career interests. - Candidate should have previous experience of providing placement to students in the aviation and manufacturing organizations. - Assist students in all aspects of the job search including resume writing, interviewing techniques and job referrals. - Schedule and follow up on student interviews with prospective employers from the aviation industry. - TPO needs to keep in touch with professionals from different Airlines in order to stay updated with the new job vacancies that come up. - Counsel, prepare and enhance hiring potential of students. - Ability to bring onboard Guest Lectures and handling Training programe and enabling right internship to the Students - Developing and executing the placement strategy. - Conducting recruiting survey. - Coordinating all the activities related to placement. - Maintaining student resume bank. - Interacting with the past recruiters. - Attend seminars and other training opportunities for professional development. - Other related duties as assigned. - Good communication with pleasing personality. Preferred candidate profile Qualification - MBA /M.Tech from a reputed university. Experience - Candidates with proven track record in placements and ready to achieve the targets.

Hiring for a Placement Officer! Experience: minimum 6month in relevant field Salary: As per company norms. Location: Pune Position: 1 Joining: Immediate / 15 Days Required Skill Set: - Excellent verbal / written communication skill. - Good convincing skills - Self-Motivated and confident approach. - Assertive and hard working. - Flexible on timings. Responsibilities and Duties : Responsible for the student placements Responsible for achieving business targets through effective placements as per timelines. Regularly follow up with student for placement related information Maintaining a database of new and existing students Arranging seminars and workshops. Interested Candidate, please share their updated CV on phulsinge@sevenmentor.com Contact on: +91 9172939470 Regards, HR Team

To Apply : Interested candidates can send their CV to anujab@itm.edu or contact Anuja- 8657547930/ Karishma- 8433973130. Location : Navi Mumbai Organization : ITM Group of Institutions Website : www.itm.edu Work Schedule : Working Days : 6 days a week (2nd & 4th Saturdays and all Sundays off). Shift : General Shift (8 hours and 30 minutes). Position Overview : ITM Group of Institutions is looking for a dynamic Placement Coordinator/Manager to lead and manage the placement process for our undergraduate and postgraduate students. This role requires strong corporate relations, strategic thinking, and the ability to manage end-to-end logistics for campus placements and corporate engagement. Key Responsibilities : Campus Placements : Drive the placement process for students across various graduate programs, ensuring successful placements across diverse industries. Corporate Engagement : Build and maintain relationships with at least 500 top-tier companies (Recruitment Heads, Talent Acquisition Heads, CXOs, Directors, etc.) for student placement opportunities. Placement Targets : Achieve placement targets, PPOs (Pre-Placement Offers), and internships for students enrolled in various programs. Logistics Management : Oversee the logistics for both on-campus and off-campus placements, including facilitating interviews, coordinating with student placement committees, and managing the overall process. Corporate Relations : Engage with corporate partners not only for placements but also for other opportunities such as guest lectures, workshops, seminars, and corporate events. Consultative Selling : Work with companies to understand their training and development needs, offering solutions related to Executive Education and other institutional programs. Strategy Development : Formulate and implement sales strategies to maximize placement opportunities for students. Student Development : Ensure that students receive soft skills training, personality development, and grooming sessions to enhance their employability. Record Keeping : Maintain detailed records of the placement process, including placement MIS, offer letters, and other related documentation. Audits : Responsible for placement audits and ensuring compliance where required. Alumni Relations : Manage relationships with alumni to support future placement opportunities. Team Management : Lead and manage a team, especially for senior-level placements.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. * Hands on PD execution at block/SoC level along with PPA improvements * Strong understanding of the technology and PD Flow Methodology enablement. * Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them * Provide tool support and issue debugging services to physical design team engineers across various sites * Develop and maintain 3rd party tool integration and productivity enhancement routines * Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set * Strong programming experience & Proficiency in Python/Tcl/C++ * Understand physical design flows using Innovus/fc/icc2 tools * Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory * Basic understanding of Timing/Formal verification/Physical verification/extraction are desired * Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory*

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 7+ years of experience in Physical Design/Implementation Minimum : Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 8 to 12 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic /PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As a CPU Physical Design Methodology Engineer, you will work with implementation and CAD teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows for next generation CPUs. : Bachelor's/Masters degree in Electrical Engineering with 5+ years of practical experience Experience with Synthesis, place and route and signoff timing/power analysis. Knowledge of high performance and low power implementation techniques Proficiency in scripting (TCL, Python, Perl) Preferred qualifications Experience in deep submicron process technology nodes is strongly preferred. Knowledge of library cells and optimizations. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good data analytical skills to identify and root cause physical design issues. Roles and Responsibilities Work with cross functional teams (RTL, Physical design, Circuits, CAD) to solve key physical design problems in CPU implementations. Develop innovative techniques in Physical design and optimization space to help meet aggressive PPA targets. Work with all external CAD tool vendors and internal CAD teams to identify and improve optimization issues related to CPU designs. Work with all block level implementation teams to analyze, implement and improve the optimization method as it pertains to the designs.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelors or Masters degree from a top-tier institute. 6-11 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job : Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelors or Masters degree from a top-tier institute. 3 to 10 years of experience in physical design from product-based companies with some leadership experience. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job : Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. Join QCOM Technologies Inc Global Emulation(Prototyping) team delivering solutions for design of leading-edge wireless products. Qualcomm is leading 5G innovations ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. The Qualcomm Global emulation team is currently seeking a lead engineer role for our team doing development/validation of large scale FPGA emulation tools/flows/methodologies In this role, you will be working in multiple areas of SoC/IP prototyping flows and methodologies. Would also involve enabling execution teams doing SOC prototyping during their usage of the platform Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 4-7 years of experience working in FPGA Synthesis, Prototyping of SoCs & IPs Candidates are expected to have experience in: Prior work experience on Emulation/Prototyping Platforms (HAPS, VPS, Protium etc) Multi-FPGA prototyping flow, from RTL preparation to h/w implementation Proficient in analysis & debug of issue in Synthesis, Place and Route, Timing closure, Clocking. Hands on experience in FPGA h/w debug using probes/ILA Proficient in EDA tools like - Vivado, Synplify, Protocompiler, VPS, VCS/Verdi etc RTL coding and simulation Well versed with working in unix/linux environment, using GVIM/VI editors, shell scripting Strong debug skills, aptitude to learn and resolve complex issues Experience in one or more scripting language - TCL, Python, Perl, Shell etc Sound knowledge of: FPGA architecture preferably Xilinx (ultrascale), Vivado IP catalog Synthesis, Timing concepts and SDC constraints Prototyping concepts like - partitioning, pinmux

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 4+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 4+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux- Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux- Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 3+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux- Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Integration CAD engineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomms class-leading Oryon CPU cores . You will build and support agile flows and methodologies that enable the first time right development of products with industry-leading power, performance and area. Experience 6 to 15 years of experience with good academics . Roles and Responsibilities Work closely with worldwide cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD Develop, integrate and release flows and methodologies for floor planning, power planning, pin placement, chip assembly, PDV analysis Develop and maintain unit and system tests to enable correct-by-construction floorplans and physical layouts Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain and support implementation flows, and resolve project-specific issues Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science 10+ years of hands-on experience in development of high-performance chips - either in a design or CAD role High level of programming proficiency ( Python and TCL ). Knowledge of data structures and algorithms Experience with automation Experience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation

Role Overview We are seeking a dynamic leader who will oversee and execute the strategic vision for placements, combining strategic planning, operational excellence, and team management. This role includes responsibilities as the Head of Placement to create a streamlined and impactful placement process for learners. Responsibilities Strategic Leadership & Team Management: Develop and execute a business plan aligned with enterprise business goals to achieve placement targets. Lead and coach a team of Placement Managers across multiple centers to continuously improve placement services. Drive the team to meet or exceed annual placement targets, ensuring operational efficiency and adherence to SOPs. Establish a culture of adherence, quality, and professionalism across the placement teams. Employer Relationship Management: Cultivate and maintain strong relationships with recruiters, local and national accounts, to generate placement opportunities. Identify hiring needs and preferences of employers, presenting EduBridge as a reliable talent provider. Ensure smooth onboarding of new recruiters, including process setup and governance. Student Relations & Placement Support: Engage with learners to address queries, provide career counseling, and build a positive outlook on available opportunities. Prepare students for interviews through counseling, mock sessions, and skill assessments. Ensure students are well-informed about TAFs (Talent Acquisition Frameworks) and apply for suitable roles. Operational Excellence: Ensure timely closures of placements within defined TAT(Turnaround Time). Maintain accurate records of placement statistics and generate performance reports for strategic decision-making. Organize cross-functional meetings to share updates and foster collaboration among teams. Networking and Industry Outreach: Attend job fairs, industry events, and networking functions to expand the employer network. Collaborate with placement agencies and industry professionals to create additional opportunities. Qualifications: Education: Graduate in any discipline or MBA (preferred). Experience: 9+ years of proven success in placements, business development, or talent acquisition consultancy. Industry Knowledge: Familiarity with IT, BFSI, or related industries. Technical Skills: Proficiency in MS Office, database management systems, and digital media strategies. Behavioral Competencies: Achievement orientation, client focus, collaboration, and effective leadership. Functional Competencies: Strategic planning, analytical skills, relationship management, and networking expertise. Values & Culture: Student First: Strive to deliver high-quality placement services and meet client expectations. Teamwork: Collaborate respectfully across teams to achieve organizational goals. Quality: Maintain superior quality in placements, services, and data. Ethics: Adhere to the highest ethical and professional standards. Expectations on Team Management: Drive employee engagement and ensure retention by creating a supportive and inclusive environment. Conduct data-driven performance reviews and provide constructive feedback to team members. Key Performance Indicators: Achievement of placement targets within deadlines. High ratio of paid placements and quality job opportunities. Robust employer and student satisfaction rates. Effective team management and adherence to organizational values. Job Description: Lead Placement Position: Lead Placements Location: Marol, Mumbai About the Organization: EduBridge Learning is a workforce development and skilling organization with 50+ training centers across 18 states in India. Over the past decade, we have empowered semi-urban and economically underprivileged youth through life skills, industry-specific training, and successful placements in 500+ companies. Vision: To be the first-choice provider of high-quality skills and career development in every corner of India. Mission: To empower youth to impact Indias future by walking with them towards a better life. Role Overview We are seeking a dynamic leader who will oversee and execute the strategic vision for placements, combining strategic planning, operational excellence, and team management. This role includes responsibilities as the Head of Placement to create a streamlined and impactful placement process for learners. Responsibilities Strategic Leadership & Team Management: Develop and execute a business plan aligned with enterprise business goals to achieve placement targets. Lead and coach a team of Placement Managers across multiple centers to continuously improve placement services. Drive the team to meet or exceed annual placement targets, ensuring operational efficiency and adherence to SOPs. Establish a culture of adherence, quality, and professionalism across the placement teams. Employer Relationship Management: Cultivate and maintain strong relationships with recruiters,local and national accounts, to generate placement opportunities. Identify hiring needs and preferences of employers, presenting EduBridge as a reliable talent provider. Ensure smooth onboarding of new recruiters, including process setup and governance. Student Relations & Placement Support: Engage with learners to address queries, provide careercounseling, and build a positive outlook on available opportunities. Prepare students for interviews through counseling, mock sessions, and skill assessments. Ensure students are well-informed about TAFs (Talent Acquisition Frameworks) and apply for suitable roles. Operational Excellence: Ensure timely closures of placements within defined TAT (Turnaround Time). Maintain accurate records of placement statistics and generate performance reports for strategic decision-making. Organize cross-functional meetings to share updates and foster collaboration among teams. Networking and Industry Outreach: Attend job fairs, industry events, and networking functions to expand the employer network. Collaborate with placement agencies and industry professionals to create additional opportunities. Qualifications: Education: Graduate in any discipline or MBA (preferred). Experience: 9+ years of proven success in placements, business development, or talent acquisition consultancy. Industry Knowledge: Familiarity with IT, BFSI, or related industries. Technical Skills: Proficiency in MS Office, database management systems, and digital media strategies. Behavioral Competencies: Achievement orientation, client focus, collaboration, and effective leadership. Functional Competencies: Strategic planning, analytical skills, relationship management, and networking expertise. Values & Culture: Student First: Strive to deliver high-quality placement services and meet client expectations. Teamwork: Collaborate respectfully across teams to achieve organizational goals. Quality: Maintain superior quality in placements, services, and data. Ethics: Adhere to the highest ethical and professional standards. Expectations on Team Management: Drive employee engagement and ensure retention by creating a supportive and inclusive environment. Conduct data-driven performance reviews and provide constructive feedback to team members. Key Performance Indicators: Achievement of placement targets within deadlines. High ratio of paid placements and quality job opportunities. Robust employer and student satisfaction rates. Effective team management and adherence to organizational values.

About the job Urgent Hiring person should have at least 5 to 10 years of experience In campus placement in University/Institutions . And can relocate to Bareilly. Job Description Purpose of the Job : To get new clientele for CRC / University for purpose of students placements & Internships. Roles and Responsibilities: Strategic and achieve successful career outcomes for the graduating class through a robust campus recruitment process. Achieve individual targets assigned for the annual recruitment process, summer internships and live projects. Support other team members wherever required. Convert new accounts through structured market outreach. Plan and engage with corporate for strategic activities including guest lectures, panel discussions, conclaves, workshops, competitions, etc. Manage and support student career services, including career counselling, grooming and helping in the preparation of students for facing interviews. Work with key stakeholders including Alumni, Faculty, Administration, Marketing & Admissions teams to achieve both career services and larger institutional objectives. Well networked in the corporate HR community. Experience in working with senior professionals in HR and functional leaders, having a track record of closing the deals. Achieving Placement and Internship targets. Create new placement partner’s basis placement load across schools and managing existing placement partners for repurchase of placements, internships Student counselling sessions in house for graduation outcomes. Corporate Engagement activities like Guest Lectures, Student Training's, Conclaves, Workshops etc. Qualification: Post graduate from any stream. Key Skills: Excellent communication skills (Spoken and written) High Integrity Knowledge of Industry demographics will be an advantage. Selection Process- Send resume at recruitment@invertis.org

Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today's market. Your role and responsibilities Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC.. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) Good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PYTHON, PERL ,SKILL and/or TCL

Position Title: Placement Officer Location: Coimbatore, Chennai, Hyderabad Department: Career Services/Placement Cell Position Summary: The Placement Officer is responsible for connecting students/clients with suitable employment opportunities by fostering relationships with potential employers, coordinating job fairs, providing career counseling, and facilitating the placement process. The role requires a combination of networking skills, administrative abilities, and a deep understanding of the job market. Key Responsibilities: 1. Employer Relationship Management: • Develop and maintain partnerships with local, national, and international employers to create job opportunities for students/clients. • Regularly communicate with employers to understand their hiring needs and preferences. • Organize employer visits, networking events, and employer information sessions. 2. Student/Client Support: • Provide individualized career counseling and guidance to students/clients regarding career exploration, resume writing, interview preparation, and job search strategies. • Conduct workshops and seminars on topics such as resume building, networking, and professional etiquette. • Assist students/clients in identifying suitable job opportunities based on their skills, interests, and career goals. 3. Placement Coordination: • Manage the placement process from initial contact with employers to final placement of students/clients. • Coordinate recruitment drives, job fairs, and on-campus interviews. • Maintain accurate records of job postings, applications, interviews, and placements. 4. Continuous Improvement: • Stay updated on industry trends, labor market information, and best practices in career services. • Seek feedback from students/clients, employers, and other stakeholders to enhance placement processes and services. • Collaborate with colleagues to develop and implement innovative initiatives to support career development and placement success. Qualifications: • Bachelor's degree in [relevant field]. Master's degree preferred. • 4 years of experience in career counseling, recruitment, or related fields. • Strong interpersonal and communication skills. • Ability to build and maintain professional relationships with diverse stakeholders. • Excellent organizational and multitasking abilities. • Proficiency in Microsoft Office and database management. • Knowledge of career development theories and counseling techniques. • Demonstrated commitment to diversity, equity, and inclusion. Interested candidate kindly share your resume to: kevin.raj@iexcel.in Contact Number: 6361047637

The Talent Acquisition Specialist will be responsible for all aspects of sourcing and hiring to fill the technical & nontechnical positions by partnering with various functions across the organization. The TA Specialist will be responsible for hiring and recruiting top talent for the organization. Essential Functions Collaborating with hiring managers to gain an understanding of open roles, review and modify job descriptions. Develops applicant flow for positions across the various functions through the following methods: Networking with industry contacts & competition mapping to source relevant candidates. Participating in Campus Placements, Job Fairs & and Industry Conferences Drafts & posts recruitment advertisements in the most effective digital, social and/or print media. Interacting with search firms and employment agencies as needed. Negotiates contracts per company standards. Identifies the most effective methods for recruiting and attracting candidates. Actively looks for innovative ways to reduce days-to-hire. Source relevant profiles using a variety of channels viz: job boards, social media, internal database, mass mailing, references, competition mapping etc. Identifies appropriate candidates and assess candidates to ensure qualification match, cultural fit, and compatibility. Pre-screen candidates as per the job description, scheduling interviews, offer negotiation & pre-offer formalities. Coach hiring managers on interviewing and selection of top talent. Build and maintain a talent pipeline of qualified IT professionals for current and future hiring needs. Maintain accurate candidate information in the applicant tracking system (ATS) and other recruitment tools. Keeping track of recruitment KPIs, preparation of weekly and monthly TA reports etc.