Physical Design Engineer

You are a Senior Physical Design Engineer with at least 6 years of experience, and your primary responsibility will be to lead the physical implementation of advanced semiconductor projects. Your role is crucial in shaping the silicon realization of cutting-edge designs, ensuring successful integration from RTL to tape-out. Your responsibilities include providing technical guidance and mentoring to physical design engineers, interfacing with front-end ASIC teams to resolve issues, and working on low power design techniques such as Voltage Islands, Power Gating, and Substrate-bias. You will also be responsible for timing closure on DDR2/DDR3/PCIE interfaces and have excellent communication skills. Your strong background in ASIC Physical Design, including floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, will be essential. You should have extensive experience and detailed knowledge in Cadence, Synopsys, or Magma physical Design Tools, as well as expertise in scripting languages like PERL and TCL. Additionally, you should have a strong Physical Verification skill set and experience in Static Timing Analysis using Primetime or Primetime-SI. In terms of required skills, you should be proficient in top-level floor planning, PG Planning, partitioning, placement, timing optimization, SI aware routing, and ECO tasks. Experience with 65nm or lower node designs with advanced low power techniques is necessary. Proficiency in EDA tools for floor planning, place and route, clock tree synthesis, and physical verification is also required. A Bachelors or Masters degree in electronics engineering or a related field is essential. Desired skills include familiarity with EDA tools such as Cadence Innovus, Synopsys ICC, and Mentor Calibre, as well as knowledge of low power design techniques and implementation.,