Physical Design Engineer

10 - 15 years

10 - 15 Lacs

Posted:2 days ago| Platform: Foundit logo

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Work Mode

On-site

Job Type

Full Time

Job Description

We are seeking a skilled and highly motivated Physical Design Engineer to join our team. The ideal candidate will be responsible for the independent planning and execution of the entire Netlist-to-GDSII flow, demonstrating a strong understanding of all physical design aspects and methodologies. This role requires technical expertise, problem-solving abilities, and the capacity to guide junior engineers.

Roles and Responsibilities:

  • Responsible for

    independent planning and execution of the Netlist-to-GDSII

    flow.
  • Demonstrate strong exposure to all aspects of design flows, including

    floor planning, placement, Clock Tree Synthesis (CTS), routing, crosstalk analysis, and physical verification

    .
  • Possess good exposure to

    high-frequency design convergence

    and a solid understanding of

    physical design methodology

    .
  • Work independently in all areas of

    RTL to GDSII implementation

    .
  • Exhibit the ability to

    collaborate effectively and resolve issues

    related to constraints validation, verification, Static Timing Analysis (STA), and overall physical design.
  • Apply knowledge of

    low power flow

    concepts such as

    power gating, multi-VT flow, and power supply management

    .
  • Possess

    circuit-level comprehension of time-critical paths

    within the design.
  • Utilize

    Tcl/Perl scripting

    for automation and efficiency.
  • Be willing to

    handle technical deliveries

    and provide guidance to a team of engineers.
  • Be well-versed with

    level timing closure (STA)

    , various

    timing closure methodologies

    , and

    ECO (Engineering Change Order) generation

    for predictable convergence.
  • Be well-versed with

    parasitic extraction, LVS (Layout Versus Schematic)/DRC (Design Rule Checking)

    , and other

    Physical Verification checks

    .
  • Provide

    clear directions to the team

    regarding

    Place & Route (PNR) issues

    .
  • Understand

    deep sub-micron design problems and solutions

    , including

    leakage power, signal integrity, and DFM (Design For Manufacturability)

    .

Education:

  • B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics

    engineering.

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