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Memory Layout Engineer

Memory Layout Engineer

Insemi Technology Services

4 - 9 years

|

20 - 25 Lacs

Bengaluru

Posted:6 hours ago| Platform:

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Skills Required

cmos sta vlsi design physical design primetime lvs icc timing analysis floorplan physical verification routing virtuoso floor planning signal integrity cadence virtuoso drc timing closure pnr leadership placement tcl analog layout

Work Mode

Work from Office

Job Type

Full Time

Job Description

Responsible for Memory Compiler layout development and verification.
Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.
Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.
Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
Guide junior team-members in their execution of Sub block-level layouts & review their work.
Contribute to effective project-management.
Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

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Insemi Technology Services

Insemi Technology Services

Information Technology

Silicon Valley

50-100 Employees

7 Jobs

Key People

John Doe

CEO
Jane Smith

CTO
Michael Johnson

COO

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