27 Finfet Jobs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelors or master’s in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools – Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages – , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full-chip layout integration and support post-layout simulations. Qualifications: 8+ years of experience in analog/mixed-signal/RF IC layout. Strong expertise in FinFET (e.g., 16nm, 7nm, 5nm) or advanced CMOS nodes. Hands-on experience with Cadence Virtuoso, Calibre DRC/LVS, and Mentor Graphics tools. Knowledge of high-frequency layout techniques, parasitic-aware layout design, and shielding strategies. Experience in power management, high-speed SerDes, RF front-ends, or ADC/DAC layouts is a plus. Proven ability to lead teams, review layouts, and drive tape-out schedules. Strong understanding of wafer-level packaging and chip integration. Excellent problem-solving and communication skills.

• Physical Design of blocks & handle Complex block implementation. • Floorplan optimization for area, Power & Timing. • Block-level PnR & close Design to meet Timing, area & Power constraints. • Implement ECOs to fix timing, noise & EM-IR violations. Required Candidate profile * Exp in RTL Synthesis for PnR using small geometry FinFET. * Strong in Physical Design incl. physically aware Synthesis, floor-planning, PnR * Logic equivalency RTL2Synthesis & Synthesis2APR netlist.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (16+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (8+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities.

With this position you will be in our Technical Ladder: a special career path for those who share innovative ideas, demonstrate comprehensive technical knowledge, show thought leadership, possess problem solving abilities and are able to create business value, Job Description In your new role you will: Contribute to highly complex designs in a multi-site organization covering all aspects of Structural and Physical SoC Design Be responsible for the physical design of multifarious digital SoCs Translate requirements into layout specifics using our state-of-the-art EDA tools and flows Work independently in different phases of the RTL2GDS flow: With focus on (one or many) Synthesis and equivalence check, generation of Floorplans, Placement, Clock Trees, Routing and Power Distribution Network for efficient Timing Closure with Signal Integrity and physical Sign off including Power Integrity Take physical limitation of hierarchical deep sub-micron designs into account and timely implement suitable solutions to overcome implementation issues, Tap your experience to contribute s Your Profile You are best equipped for this task if you have: A degree in Electrical Engineering, Microelectronics or a similar field At least 3-5 years of working experience in Physical Design of highly complex SoCs with sound experience in Synthesis, Place & Route and Timing Closure and involvement in FINFET technologies Know-how in technical leadership in physical design projects Sound programming skills and knowledge in scripting languages like Tcl, Perl or Python Basic experience in RTL coding Understanding of Functional Safety will be a benefit Fluent English language skills with German being an added plus Contact: Gowri Shenoy, LinkedIn #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals Be a part of making life easier, safer and greener, Are you in We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicant?s experience and skills, Please let your recruiter know if they need to pay special attention to something in ord

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor's, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers' and clients' business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 8 to 12 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic /PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications Bachelors or masters in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

You are a skilled Layout Engineer with 3-6 years of experience, specializing in Analog and Mixed-Signal IP layout. You have a background in Electronics or Electrical Engineering, holding a B.Tech or M.Tech degree. You possess a strong understanding of high-speed analog layout and have a solid grasp of CMOS and FinFET layouts. Your expertise extends to using CAD tools such as Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT. You are adapt at working independently, determining and developing solutions with minimal supervision. You frequently collaborate with senior personnel and are proactive in learning new technologies, demonstrating excellent analytical and problem-solving skills. Your strong communication skills enable effective interaction with internal development teams. What You'll Be Doing: Developing physical layout of high-speed Analog Integrated Circuits for the Analog and Mixed Signal IP group. Collaborating with a team of Analog/Mixed Signal Custom Layout Design Engineers on SerDes and Analog Mixed Signal IP blocks. Using advanced floor-planning techniques to optimize layout designs. Performing verification flows and ensuring compliance with DRC/LVS, LPE standards. Debugging and troubleshooting layout issues, utilizing your analytical skills. Providing regular updates to the manager on project status and networking with internal and external personnel. The Impact You Will Have: Contributing to the development of high-performance silicon chips that drive modern technology. Enhancing the reliability and efficiency of Analog and Mixed-Signal IP blocks. Ensuring the successful integration of high-speed signal layouts in cutting-edge applications. Improving the verification and validation processes through meticulous layout designs. Supporting the continuous innovation of Synopsys product offerings. Playing a key role in the development of next-generation electronic devices. What You'll Need: Experience in Analog Mixed-signal IP layout and verification of high-speed analog layout. Advanced understanding of Deep submicron effects and mitigation techniques. Expertise in CMOS and FinFET layouts and process technology. Familiarity with ESD and latchup layout design considerations. Proficiency in CAD tool usage, including Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT.

You're an experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL and SERDES design . You bring a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction. Your expertise covers circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive structures, and interconnect failure modes in advanced FinFET technology nodes. You excel at developing Analog Full Custom circuit macros , including PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP in both planar and FinFET CMOS technology. You thrive in collaborative environments, working closely with silicon test and debug experts to enhance quality through Sim2Sil correlation . You're also passionate about building and nurturing analog design talent to boost business impact through successful project execution. What You'll Be Doing: Leading SERDES analog design and development. Analyzing various mixed-signal techniques for power reduction, performance enhancement, and area reduction. Developing Analog Full Custom circuit macros for High Speed PHY IP in advanced technology nodes. Collaborating with silicon test and debug experts for Sim2Sil correlation. Building and nurturing a team of analog design talent. Working with experienced teams both locally and globally. The Impact You Will Have: Driving innovation in mixed-signal analog design. Enhancing the performance and efficiency of high-speed physical interfaces. Contributing to the development of cutting-edge technology in High Speed PHY IP. Improving quality and reliability through collaboration and Sim2Sil correlation. Growing the business impact by building and leading a talented team. Advancing Synopsys leadership in chip design and IP integration. What You'll Need: BE with 18+ years or MTech with 15+ years of relevant experience in mixed-signal analog, clock, and datapath circuit design. Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA, and up/down converters. Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits. Proficiency in high-speed digital circuit design and timing/phase noise analysis. Ability to create behavioral models of PLL to drive architectural decisions. Who You Are: Possessing strong fundamentals in CMOS, device physics, and sub-micron design methodologies. Experienced with PLL designs and high-speed digital circuit design. Knowledgeable in control systems, band gaps, bias, op-amps, LDOs, and feedback techniques. Experienced in LC VCO/DCO design and performance parameters of VCO. Familiar with digitally assisted analog circuit techniques. The Team You'll Be A Part Of: You'll be joining an expanding analog/mixed-signal SERDES team focused on the design and development of cutting-edge High Speed Physical Interface Development . You'll collaborate with experienced teams locally and with colleagues from various sites across the globe, fostering a truly collaborative and innovative environment.

About the Role: We are seeking a highly skilled and experienced Analog Layout Manager to lead our layout engineering team in the development of cutting-edge analog and mixed-signal ICs. This role requires deep technical expertise in analog layout, strong leadership capabilities, and the ability to deliver high-quality silicon in aggressive timelines. Key Responsibilities: Lead and manage a team of analog layout engineers to deliver high-quality layouts for analog and mixed-signal IPs (e.g., ADCs, DACs, PLLs, LDOs, PMICs, etc.) Own the floor planning, partitioning, and layout strategy for complex blocks and full chip integration. Collaborate closely with circuit design, verification, and physical design teams to optimize layout for performance, area, and reliability. Ensure adherence to foundry DRC/LVS/ANT/ERC/ESD guidelines and support closure of physical verification issues. Drive layout automation and CAD tool flows to improve efficiency and quality. Conduct design reviews and provide mentorship to junior layout engineers. Manage project schedules, resource planning, and risk mitigation strategies. Interface with external stakeholders including foundry, EDA vendors, and cross-functional teams. Required Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, or related field. 8+ years of hands-on experience in analog layout and team management. Proven track record of delivering production-quality analog/mixed-signal layouts in advanced nodes (e.g., 28nm, 16nm, 7nm, or FinFET technologies). Strong knowledge of parasitic extraction, EM/IR analysis, and layout-dependent effects (LDE). Proficient in layout tools such as Cadence Virtuoso, Calibre, Assura, and Mentor Graphics. Experience in team leadership, mentoring, and performance management. Excellent communication, documentation, and project management skills. Preferred Skills: Prior experience working in a fabless semiconductor environment. Knowledge of ESD protection, latch-up rules, and analog reliability concerns. Exposure to automotive, medical, or other high-reliability standards is a plus. What We Offer: Competitive compensation and benefits. Opportunity to work on leading-edge semiconductor technology. Collaborative and inclusive work environment. Professional development and career growth. Interested candidates can share their resumes to shubhanshi@incise.in

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic SKILL/PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

Requirement : Analog Circuit Design Lead Experience Range : 7 - 12 Yrs. Work Location(s) : Bengaluru, Karnataka Candidates who are ready to join Immediately Requirements: Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization. Must have led the entire Analog IP development cycle and team. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Analog/custom layout design in advanced CMOS process. Ability to understand design constraints and implement high-quality layouts. Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...). Characterization . Hands-on experience on lower FINFET technology nodes and design/PPA trade-offs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Bachelors or Masters in Electrical Engineering, Computer Science, or related field. 2+ years of industry experience in CAD or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational Requirements RequiredBachelor's, Electrical Engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelors or masters in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational Requirements RequiredBachelor's, Electrical Engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

What are we seeking- Our Technology Solutions Sales organization (TSS) hoping you as a dynamic technical professional would be a great fit as an Applications Engineering Manager (AEM) leading a growing team of dedicated field applications engineers in Siemens EDA's Bangalore office. This is both a deep leadership role and one that requires business approach, a strategic understanding of the market, and a flexible approach to tactical field execution. You will also need to remain highly organized in a constantly evolving environment, balance multiple considerations in quick decision-making and prioritization situations, and manage professional relationships inside and outside the organization. We are looking for a successful Aprisa AEM who will work with customers and potential customers to identify technology or operational challenges in their existing physical design flows, and then use developing relationships and deep knowledge to lead the Siemens team to a successful evaluation, sale, and deployment of Aprisa to solve the customers' problems. About the role! Lead recruitment, training, and development to build a strong and collaborative team of applications engineers and support staff. Own the territory technical engagements. Be the arbiter of quality, lead with vision, and collaborate with peers and management on strategy to ensure that the products are successful in your area and beyond. In collaboration with colleagues globally, develop standard processes and deliver training for the field applications engineers supporting pre-sales and post-sales engagements. Manage relationships with multiple levels of management within customer businesses. Manage Aprisa customers' technical support activities, including assessing how company products meet customer needs, and providing feedback to production engineering and R&D teams. Facilitate multi-functional collaborations regarding accounts, technical campaigns, and technology enablement with sales, management, and product teams. Provide pre-sales technical support in sales presentations and product demonstrations to active and prospective customers. Contribute to the development of content for these activities in collaboration with colleagues worldwide, product managers and marketing teams. Contribute towards the area technical sales plan with management and build/review account technical plans. Communicate frequently with peers and management on progress and account status. This is What Gives You an Edge: You're enthralled with technology but entrepreneurial-minded. You love understanding why people value (or don't) certain technologies, especially enjoy changing their minds. Lead with compassion, understanding that people who are inspired to objectives perform better and stay happier than those who are told what to do. You value building teams and organizations, taking pride in the success of others and considering your own success and growth to be inextricably linked to that of the people with whom you work. Particularly valuing the ongoing challenge of helping disparate people find their place on a team, ensuring they feel valued and are able to provide value in a way that both fits their capabilities and your needs. The experience of uncovering information about what someone needs or believes they need is fun and intriguing. Revel in aligning those expectations with what your company can deliver and becoming their trusted advisor and go-to expert. Find leading campaigns to closure rewarding, not just in the final stages, but throughout. Ensuring that technical sales campaigns are well-designed, on-track, and ultimately successful is a complex task involving communication, strategy, and administration: this all appeals. Enjoy talking to people. Guide your colleagues to success by framing problems effectively and collaborating to reach solutions. Lead with empathy. These skills translate among customers and co-workers equally. Face each challenge methodically and optimistically to increase success and handle risks appropriately. In the end, you believe firmly in results. Qualifications/Experience Required- BTech & M.Tech or equivalent experience, is an advantage Proven experience of 12 or more years in product support, applications engineering or a similar role in EDA or the IC design space Previously held leadership or direct supervisory role and demonstrated skills and attitude to encourage your direct reports Expertise in RTL to tape-out digital implementation, including synthesis, place-and-route, PPA closure, and related sign-off verification. This comes with an in-depth knowledge of FinFET-related PPA and time-to-results challenges as well as an understanding of the digital implementation tool market, industry operation, and driven offerings Enjoy working with customers and multi-functional sales, marketing and R&D teams, developing relationships and collaborating to achieve common goals

Experience Required: 8+ years to 10+ Education: Btech/Mtech Electronics/Electrical engineering Skills/Experience: Experience in Analog Mixed-signal DDR/HBM IP layout and verification of high-speed digital layout and solid understanding of high speed signal Experience in managing the technical aspects of project execution, ensuring timely delivery maintaining high quality standards, Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller, Good understanding of ESD and latchup layout design considerations, Familiarity with ASIC physical design flow: LEF generation, Place & Route & understanding of top level verification flow, DRC/LVS, LPE, Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc Scripting skills for layout automation is a plus Remote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership, Excellent written and verbal communication skills in interactions with customers, and internal development teams, Responsibilities: High Speed DDR/HBM Layout design Lead the layout design, development and implement technical solutions, Provide subject matter expertise & technical leadership in High Speed design such as DDR/HBM, Work with DDR PHY team, package engineers and system engineers to meet design specs, Perform scheduling duties, Remote site interaction etc Work with local team to support critical layout and floorplanning requirements Coordination duties with other layout teams both in Bangalore and globally, to detail out layout activities and obtain layout deliverables This includes reviewing and quality checking from remote Layout teams, Strict flow adherence and policing of internal policies to secure schedules,

Alternate Job Titles: Senior Layout Design Engineer Analog Mixed-Signal Layout Engineer Staff Engineer, Layout Design We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with over 6 years of experience in Analog Mixed-Signal layout and verification You possess a robust understanding of deep submicron effects and mitigation, advanced tool usage, floor-planning, and routing Your expertise extends to CMOS and FinFET layouts and process technology in 28nm and below You are familiar with the layout design flow, including top-level verification flow, DRC/LVS, LPE, and have a good grasp of basic ESD and latch-up layout design considerations You understand power routes, EM and IR considerations, and DFM You have exposure to Analog/Mixed Signal circuit layout (e-g , RX, TX, PLL) Your excellent written and verbal communication skills enable you to interact effectively with internal development teams You are passionate about technology and thrive in a collaborative environment where your skills contribute to groundbreaking innovations, What Youll Be Doing: Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs, Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability, Utilizing advanced tools and methodologies to mitigate deep submicron effects, Conducting floor-planning, routing, and top-level verification, Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations, Optimizing power routes and addressing EM and IR considerations for robust designs, The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components, Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments, Ensuring seamless integration and functionality of our IPs in diverse applications, Improving design efficiency and manufacturability through advanced layout techniques, Contributing to the success of our product development lifecycle by delivering high-quality designs, Supporting our mission to lead in chip design and IP integration, shaping the future of technology, What Youll Need: 6+ years of experience in Analog Mixed-Signal layout and verification, Advanced understanding of deep submicron effects and mitigation techniques, Proficiency in using advanced layout design tools and methodologies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below, Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE, Who You Are: You are detail-oriented, methodical, and have a deep understanding of layout design principles Your ability to communicate effectively and work collaboratively with cross-functional teams is exceptional You are proactive, always looking for innovative solutions to complex problems, and your passion for technology drives you to stay updated with the latest industry trends and advancements, The Team Youll Be A Part Of: You will be part of a dynamic and innovative team focused on developing high-performance Analog Mixed-Signal layouts Our team collaborates closely with other engineering departments to ensure the seamless integration and functionality of our IPs We value creativity, continuous learning, and a collaborative spirit to push the boundaries of technology and innovation, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow

Layout concepts: Good knowledge in layout matching techniques and it usage Able to do floorplan, placement , routing and lvs-drc clean at block level Hands on experience in OPAMP , LDO, BGA and reference generate blocks Handle the block independently and able to communicate with design team Expertise in EM and IR fixes Good knowledge in floor planning of IPs like RX, TX and Synth IPs Understanding of DRC errors and fixing it including density errors . Good knowledge in Tsmc 6nm technology node Interested candidates can share their resumes to shubhanshi@incise.in