DFT SMTS Silicon Design Engineer

THE ROLE:

AECG SSD ASIC is a centralized ASIC design group within AMD s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products.

As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning
• Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology.
• Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows
• Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS.
• Writing and maintain DFT documentation and specifications.
• Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.
• Performing scan insertion, ATPG verification and test pattern generation
• Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis.

PREFERRED EXPERIENCE:

• Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience.
• Demonstrated technical leadership and works well with cross-functional teams.
• Excellent communication and interpersonal skills
• Understanding of DesignforTest methodologies and DFT verificationexperience (eg.IEEE1500, JTAG 1149.x, Scan, memory BISTetc.)
• Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design.
• Understanding various technologies that must work with DFT/DFD technology such as CPU s, memory and I/O controllers, etc.
• Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
• Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
• Experience in solving logic design or timing issues with integration, synthesis and PD teams.
• Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming
• Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis.
• Knowledge of ATE and digital IC manufacturing test is a plus.
• Strong problem-solving skills.
• Team player with strong communication skills.

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering