5.0 - 9.0 years

0 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

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Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Your role and responsibilities We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design . Experience working with ATE engineers for silicon bring up, silicon debug and validation. . Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Posted 4 weeks ago

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DFT Engineer / Sr Engineer Qualcomm

1.0 - 6.0 years

1 - 6 Lacs

Chennai, Tamil Nadu, India

On-site

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Interfacewith design team to ensure DFT design rules andcoveragesare met. Generating high quality manufacturingATPGtest patterns for stuck-at(SAF), transition fault(TDF)modelsthrough the use ofon-chip test compression techniques. MBISTverification(including repair),testpattern generation through Mentor tool. ATPG(SAF, TDF)and MBISTverification usingunit delay and min/maxtiming cornersimulations. Workwith the Product/Testengineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting postsilicondebug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG,MBISTand bring-up on ATE. Developing,enhancingandmaintainingscripts as necessary Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Minimum of1-6yearsexperiencein ASIC/DFT- simulation andSilicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debugand yield enhancement In depthknowledge andhands-onexperience in ATPG-coverage analysis. In depth knowledge of Memory verification,repairand failure root-cause analysis. Experience withany of thesetoolsisrequired ATPG -TestKompress MBIST- MentorETVerify Simulation -VCS(preferred),modelsim. Expertisein scripting languages such asPerl, shell, etc is an addedadvantage Ability to work in an international team, dynamic environmentwithgood communicationskills Ability to learn and adapt to newtools,methodologies. Ability to do multi-tasking & work on several high priority designs in parallel

Posted 1 month ago

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