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Smart Soc Solutions
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Design Verification Engineer Ã¢â‚¬â€œ Position 2

Design Verification Engineer Ã¢â‚¬â€œ Position 2

Smart Soc Solutions

5 - 10 years

6 - 9 Lacs

Bengaluru

Posted:6 days ago| Platform:

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Skills Required

soc verification simulation system verilog ip gls c++ circuit soc design verification electrical engineering digital design vhdl rtl design axi fpga rtl coding ahb perl asic asic verification sv c ovm rtl uvm verilog asic design vlsi pcie eda tools

Work Mode

Work from Office

Job Type

Full Time

Job Description

Experience: 5 to 12 years
Location: Bangalore
:
We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation). Key Responsibilities:

IP and SOC Verification

Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits.

SystemVerilog (SV) and UVM Proficiency

Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and effective verification processes.

Gate-Level Simulation (GLS)

Proficiency in Gate-Level Simulation is a mandatory requirement for this position.

Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

5 to 12 years of relevant industry experience in IP and SOC verification.

Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).

Proficiency in Gate-Level Simulation (GLS).

If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of integrated circuits, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering)
Job Type Full Time
Job Location IndiaBangalore

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Design Verification Engineer Ã¢â‚¬â€œ Position 2