73 Ddr Jobs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 12+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: 10+ years of experience in the embedded domain to design, develop and support software solutions on multi-core ARM (V7A or V8A)/CPUs, Strong C/C++ programming skills. Embedded Platforms experience including low-level firmware, kernel (Linux or QNX), Hypervisor/Virtualization and user-space components. Design and development of software for heterogeneous compute platforms consisting of ARMs, GPUs, DSPs, and specialized hardware accelerators in an embedded SoC systems with J-TAG or ICE debuggers. Experience in real-time SW development for embedded products. Hands-on experience using JTAG to debug real-time problems Hands-on experience using different version control systems like perforce, GIT Expertise in Development of PCI RC/EP Device Driver. Expertise in writing kernel space device drivers in areas of MMU, Power(clocks/thermal). Solid understanding of Linux/QNX boot flow on embedded systems. Solid understanding of computer system architecture (core, cache, memory models, bus architecture, etc.). Experience in Board Bring-up, Device drivers, peripheral buses (SPI, I2C, USB), Memory controller DDR, eMMC, UFS and Performance. Solid understanding of different debug methods offered by Linux Kernel/QNX. Motivated self-starter with excellent verbal and written communication skills, demonstrated ability to work with engineers/partners/customers across different geographies. Hands-on technical lead who is not hesitant to dig into the details where needed to get first-hand knowledge of the issues and play an active and personal role in steering team success Collaborate with internal teams and external partners on analysis and debugging. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.

Responsibilities 6 to 12 years of complete hands-on experience in RTL Verification at both SoC/IP level. Should be proficient in building New or maintain existing SV/UVM/C based testbenches. Experienced in SV-UVM/OVM/VMM Methodologies. Specman hands-on can be a plus. Should have handled Complex Blocks/Hard Macro Level Functional Verification at both RTL and Gate Level. Should have experience dealing with Coverage Models and metrics issue and closure based on specification. Able to develop and track Test Plan & Validation Plans based on Specification. Able to setup Regression environments based on Test Plans. Experience in dealing GPIO, Clock Controller, DFTMUX, System controller such as PMU/CMU/TMU and power issues at SoC level will be an advantage. Knowledge on Power-Aware -CPF/UPF Simulation at both RTL and Timing Simulations at Gate Level. Able to Work closely with the Architecture, Design, Synthesis and Physical Design team teams to resolve the RTL/GLS level issues. Should have knowledge on any of the Bus interface - PCIe/USB/I2C/SPI/UART. Should have worked on AMBS protocols. Technologies: 28nm and below. Experience in Tcl/Tk, PERL, Makefile is a definite Plus. Qualifications Education: B.Tech/BE/ME/M.Tech

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Expertise in ASIC SOC verification. Expertise in UVM, System Verilog and constrained random testing. Expertise in Gate Level Simulation tools (GLS) or verification related to display port or memory controller Expertise in testbench architecture and SOC-level verification strategies. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Preferred immediate hires only Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Summary: We are seeking a highly skilled and motivated Senior Design Verification Engineer to join our growing team. You will be responsible for planning and executing the verification strategy for complex ASIC/SoC designs. You will work closely with design, architecture, and software teams to ensure functional correctness of RTL through rigorous verification methodologies. Key Responsibilities: Develop and execute comprehensive test plans based on design specifications and architectural documents. Build and maintain constrained-random verification environments using SystemVerilog UVM . Write testbenches, test cases , and functional coverage to ensure design quality. Debug RTL and testbench issues using industry-standard tools (e.g., VCS, ModelSim, Verdi, DVE). Develop and track coverage metrics (code, functional, and assertion coverage). Contribute to the automation of the verification process (e.g., regression tools, continuous integration). Participate in design and verification reviews and provide technical guidance to junior engineers. Required Skills & Experience: Bachelors or Masters degree in Electronics, Electrical Engineering, or Computer Engineering . 3Years to 25 Years of experience in RTL verification of complex digital designs. Proficiency in SystemVerilog , UVM methodology , assertions, and functional coverage. Strong debugging and problem-solving skills. Experience with simulation tools (Synopsys VCS, Cadence Incisive/Xcelium, ModelSim, etc.). Solid understanding of SoC architecture, AMBA protocols (AXI, AHB, APB). Hands-on experience with scripting (Python, Perl, Tcl, or Shell). Familiarity with version control systems (e.g., Git, Perforce). Preferred Qualifications: Exposure to PCIe, Ethernet, USB, DDR , Jtag or other high-speed interfaces. Why Join Us: Work on cutting-edge technology with top-tier semiconductor clients. Opportunity to lead verification activities and mentor junior team members. Competitive compensation and flexible work culture.

Sr Staff Engineer Design Verification [ Location: NOIDA] Job Description We are seeking a diligent Verification leader to join our team at leading semiconductor company. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities: Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers andmicroprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.

We are looking for Senior SOC Verification Engineers for Hyderabad & Bangalore location. 1) SOC Verification 2) SV UVM 4) C & Verilog Language Interested candidates, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com

WHAT YOU DO AT AMD CHANGES EVERYTHING. We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.. AMD together we advance_. PMTS SILICON DESIGN ENGINEER. As a SerDes Verification Architect, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing data integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards.. Key Responsibilities. Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).. Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.. Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.. Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.. Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.. Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.. Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.. Verification methodology: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.. Experience:. 16+ years of experience in SerDes verification or high-speed communication verification.. Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.. Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.. Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.. Skills:. Solid understanding of SerDes architectures, link training, and equalization.. Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).. Familiarity with hardware description languages (HDL) like VHDL or Verilog.. Strong analytical, problem-solving, and communication skills.. Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.. Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.. Preferred Skills. Experience with Python, Perl, or similar scripting languages for automation.. Exposure to high-speed memory interface design and verification, including DDR controller IP verification.. Functional coverage, assertions knowledge in SV/UVM.. Ability to work in a fast-paced environment and manage multiple verification tasks.. Strong team player with good interpersonal and communication skills.. Benefits offered are described: AMD benefits at a glance.. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.. Show more Show less

We aspire to be world-leader in innovative telecom and security solutions by offering cutting-edge, high-performance telecom and security solutions to business customers. Our Mission is simple. To prove that Indian engineers can design, develop, and manufacture world-class technology products for customers across the world, right from India. Join our team of like-minded engineers, applied researchers, and technocrats with the will, courage, and madness to achieve this mission! Why work at Matrix Matrix fully integrates software and hardware across its products. Engineers here collaborate more effectively to create solutions that solve real problems and make an impact. We are responsible for every nut, bolt, and line of code in our products! As an engineer, your involvement will be critical in the entire lifecycle of a product - right from ideation-development-production-deployment. Get to feel the sense of accomplishment that comes with creating something that solves a real and pressing problem and is used by scores of customers. Role Engineer/ Sr. Engineer - Hardware Design (Schematic) Function Hardware Design - (Schematic) Work Location Vadodara, Gujarat Who are you You are an energetic and passionate individual with extensive expertise in hardware design, particularly in schematic design. You possess a deep understanding of various hardware components and systems, including IP cameras, video recorders, access control systems, smart card readers, IP terminals, PABX, GSM gateways, military-grade cameras and recorders, and explosion-proof cameras. You thrive on tackling complex challenges and are driven by a commitment to innovation and excellence in hardware design. Experience 1 - 5 Years (Freshers can also apply) Qualification B .E/ B.tech/ M.E/ M.tech (EC, Electronics & Communication) OR MSc (EC/Electronics) Technical Skills Required : Experience on all stages of Hardware Product Development Lifecycle. Development of high speed board design in embedded domain. Should have hands-on experience of Schematic design. Experience on all stages of the Hardware Product Development Lifecycle. Designing and developing components such as printed circuit boards (PCB), processors, memory modules, and network components. Experience on High-Speed Interfaces like DDR, Memory, Audio, USB, Ethernet (Experience on HDMI, SATA, MIPI, CSI, USB, I2C, SPI will be additional benefit). Working experience in hardware design of Micro-ProcessorsTI, ARM CORTEX A7/A9, Freescale, NXP, Qualcomm. MemoriesDDR2, DDR3, LPDDR2/3. EMI-EMC Compliance related basic knowledge. Exposure of Design testing. Deriving H/W design requirements from EMI, EMC, Safety & Automotive EMC/Transients test standards. Preparing BOM (Bill of material) in the most efficient way. Thermal and product reliability know how. Alternate part approval and verification (Electronics components characteristics know how). How your day might look like Design block diagram and architecture for product design Create schematic diagrams following engineering layout principles and industry standards Evaluate and prepare comparison of parts Review and revise schematic designs to ensure accuracy, functionality, and alignment with project requirements. Secure approvals for component selections and design decisions from stakeholders Integration with other engineering departments for product definition (System design, Schematic and Layout integration, upfront work with vendor team). Oversee design and testing related management with structural workflow. Product certification support like CE, FCC and other safety standards Work on high-speed interfaces such as RGMII, MIPI-DSI, PCIe Gen3, MIPI-CSI, eMMC, and USB 3.0 to ensure seamless integration and performance. What we offer Opportunity to work for an Indian Tech Company creating incredible products for the world, right from India Be part of a challenging, encouraging, and rewarding environment to do the best work of your life Competitive salary and other benefits Generous leave schedule of 21 days in addition to 9 public holidays, including holiday adjustments to convert weekends into long weekends 5-day workweek with 8 flexi-days months, allowing you to take care of responsibilities at home and work Company-paid Medical Insurance for the whole family (Employee+Spouse+Kids+Parents). Company paid Accident Insurance for the Employee On-premise meals, subsidized by the company If you are an Innovative Tech-savvy individual, Look no further. Click on Apply and we will reach out to you soon!

Design Verification with SOC Experience Proficient in DDR

Key Responsibilities Schematic Capture & PCB Layout Design and optimize complex multi-layer PCBs for high-speed digital and RF applications using tools such as Altium Designer, Cadence Allegro, or OrCAD. Implement controlled-impedance routing, differential-pair tuning, power-integrity planes, and RF transmission lines. High-Speed Signal Integrity Perform SI analysis (eye-diagram, timing, crosstalk) and apply best practices for DDR, PCIe, USB3, Ethernet, HDMI, etc. Collaborate with SI/PI engineers to define stack-ups, copper pours, via types, and decoupling strategies. RF/Microwave Design – Layout antennas, filters, matching networks, baluns, and mixers for frequencies from VHF through UHF (e.g. 13.56 MHz NFC to several GHz Wi-Fi/Bluetooth/GPS). – Ensure low-loss RF paths, minimal parasitics, and effective grounding/EMI shielding. Prototype Validation & Debug – Coordinate board spins, oversee fabrication files (Gerbers, ODB++), and work with board houses on stack-up definitions. – Lead bench-level bring-up, signal probing, VNA/oscilloscope measurements, and cross-section analysis to troubleshoot issues. Documentation & Process Improvement – Produce clear build packages, assembly drawings, and manufacturing notes. – Maintain design libraries, enforce DFM rules, and drive continuous improvement for faster turnaround and higher yield. Cross-Functional Collaboration – Partner with analog/digital/RF hardware engineers, mechanical designers, firmware teams, and test engineers to ensure seamless product development. – Mentor junior designers and share best practices in layout, routing, and design for manufacturability. Required Skills & Qualifications Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field. 4+ years of hands-on PCB design experience in high-speed digital and RF domains. Proficiency in industry-standard ECAD tools (Altium, Cadence Allegro, OrCAD). Deep understanding of controlled-impedance calculations, SI/PI fundamentals, and RF layout techniques. Experience defining and validating PCB stack-ups, dielectric materials, and copper weights. Skilled in RF test equipment: network/analyzer, spectrum analyzer, VNA, and high-speed oscilloscopes. Strong documentation skills and familiarity with IPC standards (IPC-2221, IPC-7351). Preferred Qualifications Experience in wireless communications (BLE, LTE, GPS, NFC) or aerospace/defense electronics. Familiarity with thermal management, EMI/EMC mitigation, and HDI/microvia technologies. Working knowledge of DFM/DFT principles and vendor-specific fabrication processes. Previous involvement in certification processes (CE, FCC, MIL-STD).

Job Description Experience: 3 to 18 years experience. Educational Qualification: B.E./ B.Tech. in Electronics and Communication, Electronics and Telecommunication, M.E. / M.Tech. Electronics & Communication Location: Bangalore Technical/Functional Skill Set : Substantial experience in the field of FPGA based Board Design, Embedded Hardware/Board Design. Expertise in Processor, Networking, Telecommunications, Bus interfaces, DDR memories, Test plan, Board bring-up, Networking, Telecommunications, Serial interfaces, Bus interfaces, DDR Memories Board bring up and debug skills Experience in system level architecture development would be preferred. Embedded HW designs for Defence applications Exposure to qualification process Tools: Schematic capture and layout tools like Orcad/Allegro SI analysis tools Soft Skills: Good Communication Skills People Management and leadership Skills Awareness of Quality Systems. Experience in handling small group sizes and projects Managerial Skills Job Description: To develop and test designs as per the project specification. To review modules developed by the group members. Monitor and Track effort and schedule of the tasks and hardware /software items of the project that are assigned to the group. Coordinate internal project meeting with Project Manager and other Group members, to present any suggestions for improvement Monitor and ensure the quality goals of the group. Co-ordinate Configuration activities and Quality Control Activities Participate, co-ordinate, implement/monitor defect prevention and process improvement activities in the project. Resolve any technical and interpersonal issues of the group members. Assist in annual performance reviews To ensure defect free and timely deliverable as per the project plan. To ensure adherence to defined processes. To provide guidance and technical assistance to Group Members. QMS and Process Adherence Learning and Growth and Group Development

Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 3+ years of relevant experience.Strong in UVM/System Verilog/C/C++/scripting, Simulation, Formal verification. Good understanding of SoC architectures Required Candidate profile GLS verification experience at Core level. SV - UVM understanding. Scripting in perl, python. Debug of complicated designs using Verdi. Power aware verification, SDF / timing simulation.

Role & responsibilities High-speed design FPGA Based design experience (Xilinx/Intel) Intel Based Server designs Interfaces like (JESD, SFP, QSFP, I2C, SPI, USB, PCIe, etc) Memory (DDR3/4, eMMC, QSPI etc) Testing, Bring-up, and debug RF Basics (Power Amplifiers High power or Small signal RF) ADC/DAC basics SI/PI Analysis Documentation skills like Design Document Layout Guidelines creation RCA/ CAPA Block diagram creations etc.

Job Details: : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications: Bachelor Degree in Electrical and Electronics Engineering or Masters Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Description: We are looking for a Senior RTL Design Engineer with solid experience in ASIC Digital Design . The ideal candidate should possess strong expertise in RTL design using Verilog/System Verilog , with a proven background in developing complex digital designs and working on high-speed interfaces. This is a pure design-focused role ; candidates with FPGA-centric experience will not be considered . Key Responsibilities: Develop and implement RTL designs using Verilog/System Verilog . Work on SoC and IP-level designs focused on high-speed interfaces (e.g., APB, AXI, AHB, DDR, PCIe). Perform lint , CDC , RDC checks and validate timing constraints. Support post-silicon validation . Use EDA tools for simulation, synthesis, and timing analysis. Required Qualifications: Minimum 8 years of hands-on experience in ASIC RTL/Digital Design . Strong expertise in Verilog and System Verilog . Working knowledge of high-speed bus protocols: APB, AXI, AHB, DDR, PCIe . Proficient with industry-standard EDA tools . Good understanding and experience with static checks . Must have experience in ASIC Design only FPGA-focused candidates will not be considered . Interested Candidates share your resumes to priya@maxvytech.com

Job Description We are looking for Hardware Engineers who can join us in immediate. Role: Hardware Design Engineer Exp: 3 to 6 Years Education: BE /B.Tech Location: Bangalore Work mode: Work from office. We are seeking a Hardware Design Engineer with expertise in the automotive domain to design, develop, and validate electronic hardware for automotive applications. The ideal candidate should have experience in automotive electronics, circuit design, PCB design, and compliance with automotive safety standards . Required Skills: Responsible for Hardware Board design, Schematics design, Circuit design /analysis Experience in CAN protocol, IMX 68, IMX RT, RH850, Renesas, NXP Experience on Memories - DDR's, NAND and NOR Strong Knowledge on power - DC- DC Strong knowledge in Communication Protocols - I2C, UART, SPI Knowledge in Circuit Design - Capture tool(Orcad) Good to have experience in Bluetooth, GSM, WIFi Strong analog circuit simulation skills using SPICE Hands on Experience in Hardware Board design (Electrical/Electronic schematics Design) To work on the Electronics board design and analysis having microcontroller, touch, analog, relay drive, LED drive, UART/SPI ports. Good knowledge of electronic circuit design using discrete semiconductors (BJT, MOSFET, Diodes) Good knowledge of electronic circuit design using signal chain building blocks like Op-Amps Qualifications: BE / B.Tech (CSE), ME/M.Tech. (ECE/EEE/IT) or any equivalent qualification. If you find it interesting, Please share your updated resume to the below mentioned mail id nagendrababu.p@optmsol.com

Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Preferred Qualifications 5+ Year of industry experiences in the following areas: - Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5) Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Interested can share resume on Shubhanshi@incise.in

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Owning and Driving execution of subunits/unit level Verification Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Work with IBM Verification community to improve Verification methodology. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 + years of experience in Functional Verification of processors or ASICs. Minimum 9+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading teams Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification. Good understanding of the Server System

Overview Lead Verification engineer Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Bachelor’s/ Master’s degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platformsUVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Bachelor’s/ Master’s degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platformsUVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3- 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The role generally entails a mixture of: Ownership of a piece of the test bench Planning & execution of feature additions and mode re-enablement on particular variants Bug fixes Debug of regression signatures Developing/Deploying new tools for performance validation Performance monitor and profiler development and deployment Workload specific simulations on the emulator Following skillset is required: Strong Python, C++ skills Reading Specs and developing test plans Monitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening 6 months - 8 Years of industry experiences in the following areas- Basic of digital design concepts, fifo etc Basic understanding of DDR is a plus Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering Candidate must possess right analytical skills, debug oriented mindset and must be open to discuss , deep dive, collate and present the design and environment understanding . Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Skills & Experience MTech/BTech in EE/CS with 7+ years of ASIC design experience. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6) is added advantage. Understanding of protocols like AHB/AXI/ACE/CHI is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Hands on experience in Low power SoC design is required. Responsibilities Mirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules. Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels. Hands on experience in constraint development and timing closure. UPF writing, power aware equivalence checks and low power checks. Support performance debugs and address performance bottle necks. Provide support to sub-system, SoC integration and chip level debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology. Qualcomm Systems Engineers collaborate across functional teams to meet and exceed system-level requirements and standards. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. You will be part of Automotive System Performance team that is responsible for optimizing the Multimedia performance on Snapdragon Automotive chipsets. The Candidate should have at least 6-8 years of experience on Multimedia technologies comprising of Camera, Video, Graphics, and Display technologies. The candidate should be proficient in Android/Linux kernel fundamentals, Debug tools, fundamentals of interconnects, System QoS, Bus protocols and performance Monitoring. The Candidate should have the following requirements At least 6-8 years of embedded domain experience in Multimedia Hardware architecture and device driver development. Proficient in hardware fundamentals of display/Video/Camera basics, DDR, SMMU, NOC and system interconnects, AXI/AHB Bus protocols and hardware Performance Monitoring systems. Good understanding of Auto/Mobile SoC architectures and Multimedia Subsystems hardware data flows. Basics of Arm processor architecture, Multicore/Multiprocessor with SMP/heterogenous cores. Expertise in C programming language on an embedded platform is a must. Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism, MMU/paging etc. Prior working experience in IP hardware functional and performance validation in silicon and or emulation, preferably in Multimedia domain viz. camera, Video, Display, GPU and Audio. Familiar with Android System tools, Debug tools, JTAG, scripting etc. \ Passion in debugging system level issues, working with teams across geographies and partnering with cross functional teams towards meeting project milestones. Exposure to working on emulation/pre-si environment is added advantage. Responsibilities The candidate is expected to assume all responsibilities towards project execution. With good understanding of SoC Multimedia cores, candidate should be able to support activities related to System use cases profiling and optimization. The candidate will be responsible for understanding the HW setups in the lab and carrying out the performance tests. Education RequiredBachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Computer Science and/or Electrical Engineering