73 Ddr Jobs - Page 2

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Job Overview Qualcomm is leveraging its core strengths in wireless and compute technologies to lead a significant technological revolution in the automotive space. Having pioneered connected car technologies for over a decade, Qualcomm is now at the forefront of evolving Automotive Infotainment, Telematics, ADAS/Autonomous Driving, and supporting technologies. We are investing in cutting-edge technologies such as 5G, Cellular V2X, Computer Vision, and AI/Deep Learning, and are collaborating closely with global automakers, Tier-1 suppliers, standards bodies, consortiums, and operators to push the boundaries of innovation. The Qualcomm Automotive Infotainment Team is seeking a Display Architect who can make a significant impact in the automotive space and join our growing multisite engineering organization. Responsibilities Lead the design and implementation of display processing pipelines on Qualcomm's Autonomous/ADAS SoCs and platforms. Architect and develop the next-generation display stack, ensuring robust system-level integration and performance. Collaborate closely with product owners and domain/technology experts to define specifications, lead software design/implementation, and integrate/validate software in a larger system. Own the complete display driver stack development from requirements to design, development, and bug fixing. Actively engage with Automotive OEMs, Tier-1s, and ISVs to implement solutions based on Qualcomm Automotive platforms. Design complex fault-tolerant safety systems and ensure compliance with industry-standard specifications (e.g., ISO26262, ASPICE). Optimize display performance, power consumption, and system-level integration. Minimum Qualifications 13-16 years of experience in the embedded domain, designing, developing, and supporting software solutions on multi-core ARM/CPUs. Strong C/C++ programming skills. Extensive experience with embedded platforms, including low-level firmware, kernel, and user-space components. Expertise in designing and developing software for heterogeneous compute platforms consisting of ARMs, GPUs, DSPs, and specialized hardware accelerators in embedded SoC systems with J-TAG or ICE debuggers. Proven experience in end-to-end display stack development for embedded products. Solid understanding of operating systems, system-level architecture, and low-level software/hardware interface design. Preferred Qualifications Motivated self-starter with excellent verbal and written communication skills. Demonstrated ability to work with engineers, partners, and customers across different geographies. Experience working with senior management in a corporate environment. Expertise in display interface standards such as HDMI, DSI, LVDS, eDP, and FDPLINK3. Working knowledge of the Android/Linux kernel with respect to DRM/KMS/FB drivers. Thorough understanding of the Android Display/GFX architecture and display native services and framework, including multi-display. Experience with SurfaceFlinger/Wayland compositors is a plus. Educational Bachelor's or Master's Degree in Engineering from a reputed institute. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. 3+ years of work experience with Programming Language such as C, C++, Java, Python, etc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview We are looking to hire a strong DV engineer to work on verification of LPDDR/DDR based IPs and Subsystems in the Infra IP team Create DV infrastructure for verification Integrate VIP's Create and execute test plans, debug failures, write assertions, close code and functional coverage Ensure high quality verification Working with all stakeholders to ensure program success Minimum Qualifications Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field. 4+ years Hardware Engineering experience or related work experience. Preferred Qualifications Following skill set is required: Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Preferred Qualifications 4+ Year of industry experiences in the following areas- Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of DDR/LPDDR families (LP/PC) and generations (DDR2/3/4/5) Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Preferred Qualifications: We are looking for candidates who has relevant work experience in DDR SW driver development. We can target some companies which are working in embedded system DDR development like Mediatek , Intel , Micron, AMD , Samsung , Marvel semiconductor etc. Openings in DDR System team Qualcomm Hyderabad PositionLead Sr. Engineer - DDR Systems Exp:- 6+ years, DesirableDDR technology (Relevant work exp in DDR SW driver required ) Opportunity: Debug and Development of DDR init & run time driver sequences. Will be working on state-of-the-art DDR technology LP4x/LP5x. Opportunity to get the understanding of DDR technology. Will be responsible for driving multiple programs. Need to work on issues with multiple teams (performance, Phy, controller design etc.) Need to analyze lot of data and need to recognize patterns. Working on triage of the DDR issues. Test case enhancements and development Job description Minimum Qualifications The charter of the CoreBSP-DDR SW System team is to ensure that the end-product qualifies the defined acceptance criteria for DDR by meeting stability, Power, and Performance Goals . The team is looking for a candidate who has strong understating of system level test methodologies and run validations on mobile systems. The position involves Understanding of SOC Architecture and DDR SW Systems, identifying and debugging DDR systems issues ( memory corruptions, Memory Lock-ups, Bit flips, memory leaks etc..)reported by memory validation and also running system level validations tests. The engineer would have opportunity to interact with different SW & HW teams to understand DDR systems. The candidate is expected to own and drive multiple chipsets in DDR tech area. This position gives an exposure to understand various quality stages from product development to commercial launch of the product. Skills: C, Python, Embedded system , JTAG , processor architecture, RTOS operating system, core BSP driver level development and debug ,CPU architecture , SOC System knowledge. DesirableDDR technology Level of Responsibility: Works independently with minimal supervision. Decision-making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. BDC Post Silicon Engineering group has an opening for a Digital Bench characterization Engineer. This group develops Test solutions for Design verification of Highly integrated SOCs (System on Chip) designed by Qualcomm. We work with Design, System, Program Management, Yield, Reliability and Manufacturing teams to Test, support and commercialize Qualcomms products. As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge LPDDR & PCDDR Subsystem components (DRAM, DRAM Controller, DRAM PHY, IOs, PLL/DLL, clocking architecture, Delay circuits, Power Distribution Network) and High-Speed IO interfaces (PCIe, USB2/3, Display Port, HDMI, MIPI-CSI/DSI, UFS & PLL). You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of DDR & High-Speed IO IPs and perform failure analysis to root-cause a design problem. You with be working with IC design engineering, system engineering and Hardware applications engineering teams across the globe in a time critical environment. Education MTech, BTech or Equivalent in Electronics or Electrical Engineering with 1-3 years of related work experience Skills/Experience: Solid understanding of Electronics engineering fundamentals, DDR & High-Speed IO circuit analysis techniques and Semiconductor manufacturing process, Good understanding of Test and characterization methodology of DDR and High-Speed IO interfaces In-depth understanding of Mobile & PC DDR 2/3/4 protocol, timing diagrams, HSIO IPs PHY level understanding and Electrical parametric compliance specifications (eye diagram, differential signaling, jitter analysis, Receiver-Jitter-Tolerance, signal integrity, transmission line considerations, de-embedding). Hands-on experience using Bench instruments such as oscilloscopes, J-BERT, network / spectrum analyzers, signal generators and Logic analyzers is a must. Solid software skills for writing and debugging Test code using C, C# or Python. LabView knowledge is a plus. Using CAD software such as Mentor Graphics DA or Cadence Allegro is a plus. Ability to work effectively in a fast-paced environment with strong verbal and written communication skills. Keywords DDR, High-Speed IO, Electrical Spec compliance, Eye Diagram, Jitter, C, C#, Python, LabVIEW

Hot Vacancy Design Verification Engineer (5–10 Years) Location: Bangalore Experience: 5 to 10 Years Industry: Semiconductors / VLSI / ASIC Employment Type: Full Time Joining: Immediate to 30 days preferred Job Description: We are actively hiring skilled and passionate Design Verification Engineers with 5–10 years of experience for multiple cutting-edge SoC/ASIC. Roles and Responsibilities: Develop test plans , testbenches , and testcases using System Verilog and UVM . Own block-level and/or SoC-level verification and drive coverage closure . Verify protocols and interfaces such as AXI, AHB, PCIe, LPDDR5, UCIe, I3C, CXL , etc. Perform assertion-based verification (SVA) and support gate-level simulations (GLS) . Collaborate with cross-functional teams including RTL. Desired Candidate Profile: 5–10 years of hands-on experience in ASIC/SoC functional verification . Strong in System Verilog, UVM . B.E./B.Tech or M.E./M.Tech in ECE/EEE/CSE or related fields. Why Join Us? Work on next-gen chip designs with global teams. Opportunity to work on latest protocols and IPs . Interested Candidates share your resumes to priya@maxvytech.com and hr@maxvytech.com

verification experience in SV, UVM, DDR, serdes high speed protocol, PCIE

IO Design Work Location: Bangalore Experience: 5 to 15+ years In your new role you will: Technically Lead complete design & development of IO library Lead interaction with system architects of product development to close IO specifications & requirements. Drive IO integration into sub-system resolving all technical issues. Should act as an advisor (Expert support) for the IO selection/Implementations/Integration/qualification at the sub-system. Should act as an advisor (Expert support) for the IO selection/Implementations/Integration/qualification at the sub-system. Own IO quality sign-off & checklist at different milestones to ensure quality deliverables to SOC. Drive the definition of the overall concept(circuit/layout) including the sub-blocks in alignment with product requirements. Guide the team members on the effective implementation of the IOs. Review their designs and continuously drive the turnaround time, design robustness/optimizations and area/power of IOs Review their designs and continuously drive the turnaround time, design robustness/optimizations and area/power of IOs Support the design development hands-on as per the project needs. Continuous improvement and development of design and verification methodologies for improving quality and efficiency. Ensuring compliance with all Quality/Process practices for library development. You are best equipped for this task if you have: Solid experience in IO design, preferable for interface standards like LVTTL, LVCMOS, DDR, SPI, xSPI , Oscillator, LVDS , over voltage/under voltage tolerant circuits . Good understanding of ESD & LU concepts. Good understanding of the characterization methodology used in the IO library development. Candidate should be able to technically lead a team of designers/layout engineers and come up with new architectures and plan schedules. Candidate should have delivered few designs from spec to silicon with solid knowledge of associated deliverables and the development flow. Disciplined process management, problem solving skills, multi tasking ability and attention to quality and detail. Demonstrated strong analytical and problem solving skills Strong verbal and written communication skills Ability to work in teams and collaborate effectively with people in different function

Extensive experience in analog, digital, mixed-signal & high-speed hardware design. Strong knowledge of PCB design, schematic design, & selection of appropriate electronic components based on application requirements. Required Candidate profile 4+ years – 1 post - CTC 7-12LPA ; Fresher / 1 year Exp – 1 post, CTC - 4-6LPA

We are seeking a highly motivated and skilled Design Verification Engineer with a strong background in UVM, SystemVerilog , and IP-level verification . The ideal candidate will be responsible for developing and executing robust testbenches, simulation, and debugging strategies to ensure first-time-right silicon. Key Responsibilities: Develop and maintain UVM-based verification environments for IP-level testbenches. Perform RTL and Gate-level simulation and debug functional issues. Define and execute comprehensive test plans to validate functional correctness. Integrate and verify AMBA bus protocols such as AHB and AXI. Develop and close assertions and functional coverage to meet verification completeness. Write reusable SystemVerilog assertions (SVA) and functional coverage models. Collaborate with design, architecture, and verification teams to debug and resolve complex issues. Utilize scripting languages ( Shell, Perl, Python ) to automate flows and enhance productivity. Participate in regular code reviews and contribute to verification process improvements. Communicate effectively across cross-functional teams and global engineering groups. Required Skills & Experience: Strong expertise in UVM and SystemVerilog for testbench development. Solid experience in RTL and gate-level simulation and debug . Hands-on experience in test planning, writing, and executing test cases . Good working knowledge of AHB/AXI bus protocols . Proficient in assertion-based verification and coverage development/closure . Working knowledge of C programming and scripting using Shell, Perl, or Python . Excellent communication, problem-solving, and team collaboration skills. Prior experience with IP-level DV and delivery is a must. Interested can share resume on Shubhanshi@incise.in

We are seeking a highly motivated and skilled Memory Firmware Engineer to join our team and contribute to the development of cutting-edge memory solutions. In this role, you will be responsible for designing, developing, and maintaining firmware for memory subsystems, ensuring optimal performance and reliability. Key Responsibilities : Design, develop, and maintain firmware for memory subsystems, including but not limited to : - DDR4/DDR5/NVDIMM controllers - Memory initialization and training algorithms - Error correction code (ECC) implementation and management - Memory self-refresh (SR) and power management features - Advanced memory features like Secure Memory Encryption (SME), Secure Encrypted Virtualization (SEV), and Reliability, Availability, and Serviceability (RAS) - Analyze and debug memory-related issues. - Optimize memory performance and power consumption. - Collaborate with hardware and software engineers to ensure seamless system integration. - Stay abreast of the latest memory technologies and industry standards. - Contribute to the development and documentation of firmware specifications. Required Skills : Mandatory : - Very strong in C language programming and debugging - Working knowledge of git/gerrit Key Skillsets : - Good understanding of DDR4, DDR5, NVDIMM - Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) - Good understanding of UMC features like ECC, SME, SEV, RAS etc. - Experience with embedded systems development and debugging. - Strong analytical and problem-solving skills. - Excellent communication and collaboration skills.

Responsibilities : - Develop and execute comprehensive verification plans for complex IP blocks and SoCs, including microarchitecture, functional, and performance verification.- Design and implement high-quality testbenches using industry-standard methodologies (e.g., UVM, OVM).- Develop and maintain test suites, including directed tests, constrained random tests, and coverage-driven tests.- Debug and troubleshoot complex verification issues, analyze simulation results, and identify root causes of failures.- Collaborate closely with design engineers, architects, and other verification engineers to ensure timely and successful chip delivery.- Participate in design reviews and contribute to the design process.- Stay abreast of the latest verification methodologies, tools, and industry trends.- Document and report on verification progress, issues, and risks. Qualifications : - 4-7 years of professional experience in functional verification of complex digital designs (IP/SoC).- Strong understanding of digital design fundamentals and verification methodologies.- Expertise in developing and executing testbenches using industry-standard methodologies (e.g., UVM, OVM).- Experience with SystemVerilog, C/C++, and scripting languages (e.g., Perl, Python).- Good understanding of cache coherency protocols.- Experience with high-speed protocols (e.g., PCIe, DDR, Ethernet) is a plus.- Experience with UPF (Unified Power Format) and low-power simulation is a plus.- Excellent problem-solving, analytical, and debugging skills.- Strong communication and interpersonal skills.- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

Role & responsibilities Job Responsibility As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, test cases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with the RTL/uArch team. Job Requirements Experience with block level, cluster level or chip/SoC level verification. Should be a self-starter. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Post silicon support Preferred candidate profile

Key Responsibilities: Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IPs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IPs and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol Strong understanding of Coherency rules in ACE and ACE5 Experience with architecting BFMs/VIPs Should be able to handle a team of 3-4 engineers (for senior position). IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation Support in building verification infrastructure at the chip level as per the requirements Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification Strong in SV and UVM. PCIe Gen5 Tetsbench development experience is required. CXL2.0/3.0 protocol working experience will be added advantage Skills and Qualifications: Education: B.Tech/B.E. or M.Tech/M.S. in Electronics, Electrical Engineering, or a related field. Experience: 3-14 years of hands-on experience in ASIC design verification. Tools & Technologies: Proficiency in hardware description languages (Verilog, VHDL, System Verilog). Familiarity with UVM (Universal Verification Methodology) and other verification methodologies. Experience with simulation and debugging tools (ModelSim, VCS, Questa). Knowledge of scripting languages (Python, Tcl, Perl) for test automation. Experience with version control tools such as Git or SVN. Familiarity with formal verification tools and techniques is a plus. Desired Skills: Strong understanding of digital logic design, state machines, and timing analysis. Ability to work independently and collaboratively within a team environment. Strong problem-solving and analytical skills. Good communication skills to effectively report verification results and progress. Preferred Qualifications: Experience with high-level synthesis tools. Knowledge of low-power design techniques. Familiarity with performance verification and hardware-software co-verification.

About the Role: We are seeking a highly skilled and experienced Analog Layout Manager to lead our layout engineering team in the development of cutting-edge analog and mixed-signal ICs. This role requires deep technical expertise in analog layout, strong leadership capabilities, and the ability to deliver high-quality silicon in aggressive timelines. Key Responsibilities: Lead and manage a team of analog layout engineers to deliver high-quality layouts for analog and mixed-signal IPs (e.g., ADCs, DACs, PLLs, LDOs, PMICs, etc.) Own the floor planning, partitioning, and layout strategy for complex blocks and full chip integration. Collaborate closely with circuit design, verification, and physical design teams to optimize layout for performance, area, and reliability. Ensure adherence to foundry DRC/LVS/ANT/ERC/ESD guidelines and support closure of physical verification issues. Drive layout automation and CAD tool flows to improve efficiency and quality. Conduct design reviews and provide mentorship to junior layout engineers. Manage project schedules, resource planning, and risk mitigation strategies. Interface with external stakeholders including foundry, EDA vendors, and cross-functional teams. Required Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, or related field. 8+ years of hands-on experience in analog layout and team management. Proven track record of delivering production-quality analog/mixed-signal layouts in advanced nodes (e.g., 28nm, 16nm, 7nm, or FinFET technologies). Strong knowledge of parasitic extraction, EM/IR analysis, and layout-dependent effects (LDE). Proficient in layout tools such as Cadence Virtuoso, Calibre, Assura, and Mentor Graphics. Experience in team leadership, mentoring, and performance management. Excellent communication, documentation, and project management skills. Preferred Skills: Prior experience working in a fabless semiconductor environment. Knowledge of ESD protection, latch-up rules, and analog reliability concerns. Exposure to automotive, medical, or other high-reliability standards is a plus. What We Offer: Competitive compensation and benefits. Opportunity to work on leading-edge semiconductor technology. Collaborative and inclusive work environment. Professional development and career growth. Interested candidates can share their resumes to shubhanshi@incise.in

firmware development: Mandatory to have : • Very strong in C language programming and debugging • Working knowledge of git/gerrit Memory Firmware called experience level : 5-10 yrs, Key skillsets : Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc

1.Must Have: SoC or IP 2.Experience Languages : System Verilog (must) 3.Methodologies: OVM/UVM/VMM 4.Protocols:DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI 5.Processor/ARM Based SoC Verification experience 6.Candidate must have expertise in System Verilog. 7.Experience in ARM base SoC Verification 8.Strong Analytical skills desirable if having worked.

Greetings from HCL Technologies...! Experience- 5 to 12 Years Location- Bangalore/Chennai Job Description: Work on key components of functional validation of complex ASIC SOC blocks on Emulation / HAPS / Post silicon platforms Experienced in one or more of following protocols Ethernet 802.3 protocols/IP, L2/L3, PCIE, DDR/HBM, ARM/RISC-V based CPU SS, USB, Audio & DSP, AI accelerators etc. Perform Pre/Post-Silicon test content and test plan development. Regress test plan execution and infrastructure development for functional validation of complex design. Creating stress and performance scenarios to meet test plan goals. Debug failures Experienced with Source and Version Control management (GIT/Perforce/CVS etc.) Innovate to improve validation efficiency through methodologies and tools Skills: Hands on experience with C/C++ and Python is must to have. Familiarity with boards, components, memories, industry standard interfaces like Ethernet, PCIE, DDR, HBM, USB, JTAG , I2C and UART protocols . Creativity, verbal and written communication skills, analytical and problem-solving ability.

Knowledge of High-Speed Board Design Experience in designing with memories like DDR3 / DDR4 / eMMC / NAND / NOR Flash etc. Experience in designing with High-speed communication protocols like PCIe / SerDes / USB3.0 / SGMII / SFP+ /10G/100G/ Hands-on experience with MII, SGMII, RGMII, HSGMII, QSGMII, XGMII and its PHY interfaces Hands-on experience with Intel or Broadcom or Marvel or MediaTek Quad/Octal port Ethernet PHYs transceivers Should have design experience in Multiport Gigabit Network Switches, Hubs and Gigabit Router Added Advantage for knowledge of PoE 802.3at , PoE+ 802.3bt Type 2 , or PoE++ 802.3bt Type 3 or 4PPoE PoE++ Type 4 Should Have Experience of different Gbit Standard such as 1000Base – SX, 1000Base-LX, 1000Base- CX, and 1000Base-T 1Gb/s SFP(INF-8074i),10Gb/s SFP+ (SFF-8431 4.1) or 25Gb/s SFP28 (SFF-8402) and QSF,QSFP+,QSFP28 would be advantage Experience with High-speed Hardware design, Complex Analog and Digital Hardware System level design, circuit analysis, SI/PI, PSPICE simulation, Boundary scan, EMC/EMI analysis and safety standards Responsibilities include Schematic Capture, Component Selection, Library Creation and Guiding Board Layout. Should Have product development understanding like Enterprise switching, Port extender, Embedded Ethernet fabric, and TSN products Hands-on experience in Telecom/Datacom product design Experience like PDH/SDH/SONET/ and fibre optic products Should Have telecom backhaul Network transmission products design Experience, Experience in working with complex ASSPs, Microprocessors/controllers and FPGAs Experience in Signal Integrity / Power Integrity Should have worked on testing equipment like high-speed Oscilloscope, Network analysers, spectrum analysers etc

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5-7 years of experience in SOC Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-5 years of experience in SOC Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ years of experience in Design Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1+ years of experience in SOC Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Details: : Intel is a leader in the wireless communication industry, offering products that set the benchmark for performance and innovation. We are seeking a motivated Junior SerDes PHY Integration Engineer to join our team. In this role, you will focus on integrating physical layer components for high-speed SerDes systems, playing a crucial part in ensuring their performance and reliability.Key Responsibilities:SerDes PHY IntegrationsSupport the integration of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity.Simulation and ValidationAssist in conducting simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission.Calibration TechniquesHelp integrate calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission.CollaborationWork collaboratively with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system.DocumentationContribute to maintaining detailed and up-to-date documentation of design specifications, test plans, and results.Problem-SolvingAssist in addressing and resolving technical issues related to the SerDes PHY, ensuring optimal performance.Quality AssuranceSupport the implementation of quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY.Develop SERDES TestsParticipate in the development of comprehensive tests to support integration efforts, including writing scripts for software and firmware in Intel's test environment. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is a plus.Passion for lab work, collaboration, and solution development.Familiarity with scripting and programming languages such as C, C#, MATLAB, and Python.Experience in silicon development and SerDes technologies is beneficial.Strong problem-solving abilities and analytical skills.Self-motivated and capable of executing tasks in uncertain environments.Demonstrated ability to contribute effectively in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years of experience in SOC Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication.