8 Calibre Jobs

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities.

Job Specs : We are seeking a highly skilled and motivated ASIC Physical Design Experts to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Design IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location and Expertise: Bangalore : 4 Years 15 Years Beijing : 8 Years 10 Years Chennai : 3 Years 6 Years Vietnam : 8 Years 10 Years Taiwan : 8 Years 10 Years Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C / VLSI with 3+ Years of work expertise in ASIC Physical Design Expertise in managing, mentoring and training team of ASIC physical design engineers working across different time zones, this is mandatory for lead positions Expertise in ASIC PD. Expertise in digital physical design Expertise in working with 3nm & 5nm technology nodes Expertise in EDA synthesis, APR, STA tools and methodologies Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk Expertise in working with multi modes and multi corners STA Working Knowledge of multiple power planes and multiple VT libraries Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification Good at scripting languages PERL, TCL, shell Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization Expertise in making ECOs both Metal and logic level ecos Expertise in DRC and LVS cleanup of designs during sign off Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit.

Requirements Good knowledge of Standard cell layout design Good knowledge of CMOS logic Experience in working on Std cell Layout for Bulk CMOS. FINFET experience is not a must but preferable. Expertise in using industry-standard tools like cadence Virtuoso, Calibre Experience in implementation of ESD layouts, handling Antenna/EM, etc Ability to independently debug layout issues Good team player Good in SKILL programming or other scripting languages

You are a skilled Layout Engineer with 3-6 years of experience, specializing in Analog and Mixed-Signal IP layout. You have a background in Electronics or Electrical Engineering, holding a B.Tech or M.Tech degree. You possess a strong understanding of high-speed analog layout and have a solid grasp of CMOS and FinFET layouts. Your expertise extends to using CAD tools such as Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT. You are adapt at working independently, determining and developing solutions with minimal supervision. You frequently collaborate with senior personnel and are proactive in learning new technologies, demonstrating excellent analytical and problem-solving skills. Your strong communication skills enable effective interaction with internal development teams. What You'll Be Doing: Developing physical layout of high-speed Analog Integrated Circuits for the Analog and Mixed Signal IP group. Collaborating with a team of Analog/Mixed Signal Custom Layout Design Engineers on SerDes and Analog Mixed Signal IP blocks. Using advanced floor-planning techniques to optimize layout designs. Performing verification flows and ensuring compliance with DRC/LVS, LPE standards. Debugging and troubleshooting layout issues, utilizing your analytical skills. Providing regular updates to the manager on project status and networking with internal and external personnel. The Impact You Will Have: Contributing to the development of high-performance silicon chips that drive modern technology. Enhancing the reliability and efficiency of Analog and Mixed-Signal IP blocks. Ensuring the successful integration of high-speed signal layouts in cutting-edge applications. Improving the verification and validation processes through meticulous layout designs. Supporting the continuous innovation of Synopsys product offerings. Playing a key role in the development of next-generation electronic devices. What You'll Need: Experience in Analog Mixed-signal IP layout and verification of high-speed analog layout. Advanced understanding of Deep submicron effects and mitigation techniques. Expertise in CMOS and FinFET layouts and process technology. Familiarity with ESD and latchup layout design considerations. Proficiency in CAD tool usage, including Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT.

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts, floorplanning, package routing Supports complex projects or leads smaller independent design activities Support CAD and drawing updates on both sustaining/new project with minimal supervision Contributes to PD architecture/Plug-In Unit at the unit level

We are looking for a skilled EPUB Developer to join our team and work on creating, formatting, and optimizing digital books and e-learning content. The ideal candidate should have experience in EPUB development, knowledge of accessibility standards, and expertise in HTML, CSS, and XML for structured content development. Key Responsibilities: Develop and convert content into EPUB2 and EPUB3 formats, ensuring compatibility across different devices and platforms. Format and structure eBooks using HTML, CSS, and XML to maintain consistency and readability. Implement accessibility standards (WCAG, ARIA, DAISY) to ensure compliance with accessibility guidelines. Optimize and validate EPUB files using tools such as Sigil, EPUBCheck, and Adobe InDesign. Troubleshoot formatting issues and ensure proper rendering across various e-readers like Kindle, Apple Books, and Google Play Books. Convert and reformat PDFs, Word documents, and other source files into EPUB. Work closely with content developers, instructional designers, and editors to maintain quality and design consistency. Handle interactive elements like JavaScript-based widgets, animations, and multimedia (audio, video) in EPUB files. Required Skills & Qualifications: Proven experience in EPUB development and eBook formatting. Proficiency in HTML5, CSS3, XML, and JavaScript. Familiarity with EPUB validation tools such as EPUBCheck. Knowledge of fixed-layout and reflowable EPUBs. Experience with tools like Adobe InDesign, Sigil, Calibre, and Oxygen XML Editor. Understanding of DAISY, WCAG, and ARIA accessibility standards. Ability to debug and troubleshoot eBook compatibility issues. Strong attention to detail and quality control. Experience working in e-learning content development or K-12 publishing is a plus. Preferred Qualifications: Experience with Kindle Publishing (KPF, MOBI, AZW3). Familiarity with Learning Management Systems (LMS) and SCORM. Knowledge of Scripting (Python, JavaScript, or XSLT) for automation.

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow