44 Apb Jobs

Role overview: As a Cloud & DevOps Engineer, you will be responsible for implementing and managing AWS infrastructure for applications using AWS CDK and building GitHub Actions pipelines to deploy containerized applications on ECS/EKS. Must-to-Have: Hands-on experience with AWS CDK for provisioning infrastructure Solid understanding of key AWS services: ECS (Fargate), API Gateway, ALB/NLB, IAM, S3, KMS, Security Groups Strong experience with Cloud Platform engineering & DevOps Proficiency in building GitHub Actions workflows for build, containerization, and deployment Strong knowledge of Docker, container lifecycle, and CI/CD practices Understanding of basic networking (VPC, subnets, SGs) Familiarity with artifact and image management (ECR, GitHub Packages) Comfortable working in Agile or DevOps-centric environments Good-to-Have: Experience with CDK Pipelines and multi-stage deployments Exposure to GitHub Actions secrets, OIDC-based role assumption Scripting skills in Python, Bash, or Shell for automation tasks Familiarity with AWS CodeBuild or CodePipeline as alternatives Knowledge of Container orchestration in AWS, ECS and EKS for future migration planning Understanding of compliance/security frameworks and audit requirements Mandatory Competencies DevOps - CI/CD DevOps - Docker Cloud - AWS Cloud - ECS Beh - Communication Data on Cloud - AWS S3.

Role overview: As a Cloud & DevOps Engineer, you will be responsible for implementing and managing AWS infrastructure for applications using AWS CDK and building GitHub Actions pipelines to deploy containerized applications on ECS/EKS. Must-to-Have: Hands-on experience with AWS CDK for provisioning infrastructure Solid understanding of key AWS services: ECS (Fargate), API Gateway, ALB/NLB, IAM, S3, KMS, Security Groups Strong experience with Cloud Platform engineering & DevOps Proficiency in building GitHub Actions workflows for build, containerization, and deployment Strong knowledge of Docker, container lifecycle, and CI/CD practices Understanding of basic networking (VPC, subnets, SGs) Familiarity with artifact and image management (ECR, GitHub Packages) Comfortable working in Agile or DevOps-centric environments Good-to-Have: Experience with CDK Pipelines and multi-stage deployments Exposure to GitHub Actions secrets, OIDC-based role assumption Scripting skills in Python, Bash, or Shell for automation tasks Familiarity with AWS CodeBuild or CodePipeline as alternatives Knowledge of Container orchestration in AWS, ECS and EKS for future migration planning Understanding of compliance/security frameworks and audit requirements Mandatory Competencies DevOps - CI/CD DevOps - Docker Cloud - AWS Cloud - ECS Beh - Communication Data on Cloud - AWS S3

Experience :5 to 8 yrs - Senior Developer Executes software solutions, design, development, and technical troubleshooting with ability to think beyond routine or conventional approaches to build solutions or break down technical problems Creates secure and high-quality production code and maintains algorithms that run synchronously with appropriate systems Produces architecture and design artifacts for complex applications while being accountable for ensuring design constraints are met by software code development Gathers, analyzes, synthesizes, and develops visualizations and reporting from large, diverse data sets in service of continuous improvement of software applications and systems Proactively identifies hidden problems and patterns in data and uses these insights to drive improvements to coding hygiene and system architecture Contributes to software engineering communities of practice and events that explore new and emerging technologies Adds to team culture of diversity, equity, inclusion, and respect Expertise in development using Core Java, J2EE, XML, Web Services/SOA and used Java. frameworks - Spring, spring batch,Spring-boot, JPA, REST, MQ. Knowledgeable in developing RESTful micro services with technical stack, Amazon ECS ,Ec2,S3,API Gateway, amazon aurora , ALB, and Route 53 extencive knowledge and implementation experience Working with GIT/Bitbucket, Maven, Gradle, Jenkins tools to build and deploy code deployment to production environments. Hands on for CI/CD kubarnatees handas on experience Understanding modern web-based architectures and technology such as Javascript, JSON, React

Experience :8-12 yrs - Senior Lead Developer Executes software solutions, design, development, and technical troubleshooting with ability to think beyond routine or conventional approaches to build solutions or break down technical problems Creates secure and high-quality production code and maintains algorithms that run synchronously with appropriate systems Produces architecture and design artifacts for complex applications while being accountable for ensuring design constraints are met by software code development Gathers, analyzes, synthesizes, and develops visualizations and reporting from large, diverse data sets in service of continuous improvement of software applications and systems Proactively identifies hidden problems and patterns in data and uses these insights to drive improvements to coding hygiene and system architecture Contributes to software engineering communities of practice and events that explore new and emerging technologies Adds to team culture of diversity, equity, inclusion, and respect Expertise in development using Core Java, J2EE, XML, Web Services/SOA and used Java. frameworks - Spring, spring batch,Spring-boot, JPA, REST, MQ. Knowledgeable in developing RESTful micro services with technical stack, Amazon ECS ,Ec2,S3,API Gateway, amazon aurora , ALB, and Route 53 extencive knowledge and implementation experience Working with GIT/Bitbucket, Maven, Gradle, Jenkins tools to build and deploy code deployment to production environments. Hands on for CI/CD kubarnatees handas on experience

Experience :8-12 yrs Executes software solutions, design, development, and technical troubleshooting with ability to think beyond routine or conventional approaches to build solutions or break down technical problems Creates secure and high-quality production code and maintains algorithms that run synchronously with appropriate systems Produces architecture and design artifacts for complex applications while being accountable for ensuring design constraints are met by software code development Gathers, analyzes, synthesizes, and develops visualizations and reporting from large, diverse data sets in service of continuous improvement of software applications and systems Proactively identifies hidden problems and patterns in data and uses these insights to drive improvements to coding hygiene and system architecture Contributes to software engineering communities of practice and events that explore new and emerging technologies Adds to team culture of diversity, equity, inclusion, and respect Expertise in development using Core Java, J2EE, XML, Web Services/SOA and used Java. frameworks - Spring, spring batch,Spring-boot, JPA, REST, MQ. Knowledgeable in developing RESTful micro services with technical stack, Amazon ECS ,Ec2,S3,API Gateway, amazon aurora , ALB, and Route 53 extencive knowledge and implementation experience Working with GIT/Bitbucket, Maven, Gradle, Jenkins tools to build and deploy code deployment to production environments. Hands on for CI/CD kubarnatees handas on experience Understanding modern web-based architectures and technology such as Javascript, JSON, React

Role overview: As a Cloud & DevOps Engineer, you will be responsible for implementing and managing AWS infrastructure for applications using AWS CDK and building GitHub Actions pipelines to deploy containerized applications on ECS/EKS. Must-to-Have: Hands-on experience with AWS CDK for provisioning infrastructure Solid understanding of key AWS services: ECS (Fargate), API Gateway, ALB/NLB, IAM, S3, KMS, Security Groups Strong experience with Cloud Platform engineering & DevOps Proficiency in building GitHub Actions workflows for build, containerization, and deployment Strong knowledge of Docker, container lifecycle, and CI/CD practices Understanding of basic networking (VPC, subnets, SGs) Familiarity with artifact and image management (ECR, GitHub Packages) Comfortable working in Agile or DevOps-centric environments Good-to-Have: Experience with CDK Pipelines and multi-stage deployments Exposure to GitHub Actions secrets, OIDC-based role assumption Scripting skills in Python, Bash, or Shell for automation tasks Familiarity with AWS CodeBuild or CodePipeline as alternatives Knowledge of Container orchestration in AWS, ECS and EKS for future migration planning Understanding of compliance/security frameworks and audit requirements Mandatory Competencies Cloud - AWS Data on Cloud - AWS S3 Cloud - ECS DevOps - CI/CD DevOps - Docker Beh - Communication

Role: Design Verification with strong experience in ARM Experience: 4 10 years Location Bangalore or Hyderabad. Strong experience in ARM based SOCand ARM based SS level Design verification . Must have worked on ARM based SOC viz Cortex A or M series based SOC Experence in Multi processor based ARMcpu is plus Coresight Debug knowledge coresight is plus : ARM SoC based debug infrastructure including CoreSight infrastructure (implementation and/or validation). Strong debug skills with AXI/AHB/APB, memory, and NoC components. Strong work experience in AMBA AXI/AHB protocol based NOC , Understanding/ experience in CHI/ACE is plus Strong skills/Proficiencyin SystemVerilog, UVM Strong work experience(Advanced skills ) in SV-UVM and/or Cbased verification. Working knowledge in TB/Checker/SB development is plus. Must posses strong SV/UVM debugging Proficiency inC/C++ modeling. GLS experience is a plus; Should have worked on handling regressions RTL /GLS simulations and should possess excellent debugging skills Must be proactive, independent, and capable of strong simulation debug. Work Expereince or Strong knowledge in Memory SS verification - LPDDR5/LPDDR4/DDR protocols or HBMis plus Work experience in PCIe/CXL and other similar complex protocol like Ethernet is plus Scripting knowledge python, perl if worked is plus and should posses working knowledge in updating/fixing flow/pre or post processing scripts

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Lead Engineer Location: Mysore Work Type: Onsite Job Type: Full time Job Description: Should be able to build test plan, tests, coverage assertions from Specification. Architect and build testbench and testbench components. Good in UVM,SV,C SVA. Familiar with industry protocols, such as AXI, APB, AHB, PCIe, SoC. Very good in debugging. Worked with industry standard EDA tools Synopsys, Cadance simulators and debugging tools. Good to Have Skills: Experience with scripting and automation. Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, UPF-simulations, GLS and a proactive approach to automation. Exposure to SOC verification, Formal verification methodologies. TekWissen Group is an equal opportunity employer supporting workforce diversity.

About the Role: OSTTRA India The RoleSenior Network Engineer The Team The OSTTRA Technology teamis composed of Capital Markets Technology professionals, who build,supportand protect the applications that operate our network. The technology landscapeincludeshigh-performance, high-volume applications as well as compute intensive applications,leveragingcontemporary microservices, cloud-based architectures The Impact Together, we build, support, protect and manage high-performance, resilient platforms that process more than 100 million messages a day. Our services are vital to automated trade processing around the globe, managing peak volumes and working with our customers and regulators to ensure the efficient settlement of trades and effective operation of global capital markets Whats in it for you We are looking for highly motivated technology professionals who will strengthen our specialisms, and championour uniqueness to create a company that is collaborative, respectful, and inclusive to all. You will have 5-10 years experience of working with Network Infrastructure to meet the needs of our expanding portfolio of Financial Services clients .This is an excellent opportunity to be part of a team based out of Gurgaon and to work with colleagues across multiple regions globally. Responsibilities As a network engineer you will be a member of OSTTRAs global network infrastructure team that is responsible for our office, data Centre and cloud network infrastructure. You will be involved in all aspect of our network infrastructure lifecycles and work with supporting and maintaining our network. Support new projects as a network resource What Were Looking For A degree in Computer Science or a related subject or the equivalent in knowledge and work experience A minimum of 5 years of experience with networks operations and architecture. Experience with network security, firewalls, VPNs and IDS/IPS solutions. Extensive experience in protocols such as BGP and MPLS Experience from working with Juniper, Palo-Alto Networks, F5, Cisco, Fortinet. Self-motivated and great under pressure. Big-picture understanding of the networking concepts behind virtual environments and various hybrid cloud initiatives Excellent verbal and written communication skills Experience from configuration management and change management. Working experience in various AWS services such as EC2, TGW, ALB, VGW, VPC, Direct-Connect, ELB, Cloud-formation Experience using network automation tools such as Terraform, Ansible, Git and Python. Excellent AWS Troubleshooting. Experience of working with Docker and Kubernetes Experience with working with data centres in US & UK. Working experience from the financial industry. Hands-on experience of Linux operating systems. The Location: Gurgaon, India About Company Statement: OSTTRAis a market leader inderivatives post-trade processing, bringing innovation, expertise, processes and networks together to solve the post-trade challenges of global financial markets. OSTTRA operates cross-asset post-trade processing networks,providinga proven suite of Credit Risk, Trade Workflow and Optimisation services.Together these solutions streamline post-trade workflows, enabling firms to connect to counterparties and utilities, manage credit risk, reduce operationalrisk andoptimiseprocessingtodrive post-trade efficiencies. OSTTRA was formed in 2021 through the combination of four businesses that have been at the heart of post trade evolution and innovation for the last 20+ yearsMarkitServ, Traiana, TriOptima and Reset. These businesses have an exemplary track record of developing and supporting critical market infrastructure and bring together an established community of market participants comprisingall trading relationships and paradigms, connectedusingpowerful integration and transformation capabilities. About OSTTRA Candidates should note that OSTTRAis an independentfirm, jointly owned by S&P Global and CME Group. As part of the joint venture, S&P Global providesrecruitmentservices to OSTTRA - however, successful candidates will be interviewed and directly employed by OSTTRA, joiningour global team of more than 1,200 posttrade experts. OSTTRA was formed in 2021 through the combination of four businesses that have been at the heart of post trade evolution and innovation for the last 20+ yearsMarkitServ, Traiana, TriOptima and Reset. OSTTRA is a joint venture, owned 50/50 by S&P Global and CME Group. Joining the OSTTRA team is a unique opportunity to help build a bold new business with an outstanding heritage in financial technology, playing a central role in supporting global financial markets.Learn more atwww.osttra.com. Whats In It For You Benefits: We take care of you, so you cantake care of business. We care about our people. Thats why we provide everything youand your careerneed to thrive at S&P Global. Health & WellnessHealth care coverage designed for the mind and body. Continuous LearningAccess a wealth of resources to grow your career and learn valuable new skills. Invest in Your FutureSecure your financial future through competitive pay, retirement planning, a continuing education program with a company-matched student loan contribution, and financial wellness programs. Family Friendly PerksIts not just about you. S&P Global has perks for your partners and little ones, too, with some best-in class benefits for families. Beyond the BasicsFrom retail discounts to referral incentive awardssmall perks can make a big difference. For more information on benefits by country visithttps://spgbenefits.com/benefit-summaries Recruitment Fraud Alert If you receive an email from a spglobalind.com domain or any other regionally based domains, it is a scam and should be reported to reportfraud@spglobal.com. S&P Global never requires any candidate to pay money for job applications, interviews, offer letters, pre-employment training or for equipment/delivery of equipment. Stay informed and protect yourself from recruitment fraud by reviewing our guidelines, fraudulent domains, and how to report suspicious activity here. ----------------------------------------------------------- Equal Opportunity Employer S&P Global is an equal opportunity employer and all qualified candidates will receive consideration for employment without regard to race/ethnicity, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, marital status, military veteran status, unemployment status, or any other status protected by law. Only electronic job submissions will be considered for employment. If you need an accommodation during the application process due to a disability, please send an email to EEO.Compliance@spglobal.com and your request will be forwarded to the appropriate person. US Candidates Only The EEO is the Law Poster http://www.dol.gov/ofccp/regs/compliance/posters/pdf/eeopost.pdf describes discrimination protections under federal law. Pay Transparency Nondiscrimination Provision - https://www.dol.gov/sites/dolgov/files/ofccp/pdf/pay-transp_%20English_formattedESQA508c.pdf -----------------------------------------------------------

Domain : RTL FPGA SoC ASIC Design Must-Have Skills: RTL Coding, IP Design, SoC Development, Lint, CDC, Micro-architecture Protocol experience in PCIe DDR Ethernet (any one) Exposure to I2C UART SPI protocols Tool expertise in Spyglass Lint/CDC Synopsys DC Verdi Xcellium (any one)Scripting with Makeflow, Perl, Shell, Python (any one) Good to Have: Knowledge of ARM debug architecture Ability to debug across multiple subsystems Experience creating/reviewing design documentation Ability to collaborate with Physical Design, DFT, SW, and Verification teams Role Insights: Expertise in SoC Subsystem IP Design Deep understanding of RTL Quality Checks (Lint, CDC) Familiarity with Low Power Design & Synthesis Strong grasp of AMBA protocols (AXI, AHB, ATB, APB) Proficiency with multiple design & verification tools Effective communicator across multi-disciplinary teams Location : Bangalore | Hyderabad | Cochin | Pune

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 5+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Responsibilities 6 to 12 years of complete hands-on experience in RTL Verification at both SoC/IP level. Should be proficient in building New or maintain existing SV/UVM/C based testbenches. Experienced in SV-UVM/OVM/VMM Methodologies. Specman hands-on can be a plus. Should have handled Complex Blocks/Hard Macro Level Functional Verification at both RTL and Gate Level. Should have experience dealing with Coverage Models and metrics issue and closure based on specification. Able to develop and track Test Plan & Validation Plans based on Specification. Able to setup Regression environments based on Test Plans. Experience in dealing GPIO, Clock Controller, DFTMUX, System controller such as PMU/CMU/TMU and power issues at SoC level will be an advantage. Knowledge on Power-Aware -CPF/UPF Simulation at both RTL and Timing Simulations at Gate Level. Able to Work closely with the Architecture, Design, Synthesis and Physical Design team teams to resolve the RTL/GLS level issues. Should have knowledge on any of the Bus interface - PCIe/USB/I2C/SPI/UART. Should have worked on AMBS protocols. Technologies: 28nm and below. Experience in Tcl/Tk, PERL, Makefile is a definite Plus. Qualifications Education: B.Tech/BE/ME/M.Tech

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Expertise in ASIC SOC verification. Expertise in UVM, System Verilog and constrained random testing. Expertise in Gate Level Simulation tools (GLS) or verification related to display port or memory controller Expertise in testbench architecture and SOC-level verification strategies. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Preferred immediate hires only Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Responsibilities: * Collaborate with cross-functional teams on ARM processor integration. * Design, verify & debug VLSI systems using SV, UVM & GLS. * Implement IP/Sub-System/SOC architecture with APB, AXI & AHB protocols. Health insurance Provident fund

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

About the Role: Grade Level (for internal use): 09 S&P Global - Mobility The Role: TechOps Support Engineer The Team Automotive Insights leverages technology and data science to provide unique insights, forecasts and advisory services spanning every major market and the entire automotive value chainfrom product planning to marketing, sales, and the aftermarket. Technology Operations works collaboratively, both internally and across our customer base, operating in a sharing and learning culture to maintain continuous access to our products. The Impact We are seeking an experienced IT professional to join the Tech Ops support team. The role encompasses building/maintaining IT services to support existing and new product offerings for our Mobility division. Whats in it for you Candidates will work closely with Automotive teams as well as corporate IT teams in a global nature. Key area of focus include exposure to Operating Systems, Web Hosting, Networking, AWS Tools and Operations Support Responsibilities Administer AWS VPC/Applications and Security. Engage with development teams to document and implement best practice (low maintenance) cloud-native solutions. Build and deploy automation processes for Infrastructure as Service. Build and deploy automation processes for installation and patching of third-party software. Plan, build, document, and initiate disaster recovery processes. Interface with Cloud Engineering team for IT design support. Interface with IT Security team and implement security policy. Interface with Operations team to assist with troubleshooting Production Incidents and Requests. Work on initiatives and continuous improvement process around proactive application health monitoring, reporting and technical support. What Were Looking For Minimum 4+ years of work experience in an IT role and being an University Graduate with bachelors degree in computer science, related field, or equivalent experience. Knowledge of Incident management, Problem Management and Change Management. Tech Background with AWS servicesVPC, S3, CloudFront, ALB/NLB, Route 53, CloudWatch, EC2 and AWS Security Center. Hands-on activities with scripting such as Python, Terraform and Bash. In the instance there isnt an existing team, speak about the business instead. About Company Statement: S&P Global delivers essential intelligence that powers decision making. We provide the worlds leading organizations with the right data, connected technologies and expertise they need to move ahead. As part of our team, youll help solve complex challenges that equip businesses, governments and individuals with the knowledge to adapt to a changing economic landscape. S&P Global Mobility turns invaluable insights captured from automotive data to help our clients understand todays market, reach more customers, and shape the future of automotive mobility. About S&P Global Mobility At S&P Global Mobility, we provide invaluable insights derived from unmatched automotive data, enabling our customers to anticipate change and make decisions with conviction. Our expertise helps them to optimize their businesses, reach the right consumers, and shape the future of mobility. We open the door to automotive innovation, revealing the buying patterns of today and helping customers plan for the emerging technologies of tomorrow. For more information, visit www.spglobal.com/mobility . Whats In It For You Our Purpose: Progress is not a self-starter. It requires a catalyst to be set in motion. Information, imagination, people, technologythe right combination can unlock possibility and change the world.Our world is in transition and getting more complex by the day. We push past expected observations and seek out new levels of understanding so that we can help companies, governments and individuals make an impact on tomorrow. At S&P Global we transform data into Essential Intelligence, pinpointing risks and opening possibilities. We Accelerate Progress. Our People: Our Values: Integrity, Discovery, Partnership At S&P Global, we focus on Powering Global Markets. Throughout our history, the world's leading organizations have relied on us for the Essential Intelligence they need to make confident decisions about the road ahead. We start with a foundation of integrity in all we do, bring a spirit of discovery to our work, and collaborate in close partnership with each other and our customers to achieve shared goals. Benefits: We take care of you, so you cantake care of business. We care about our people. Thats why we provide everything youand your careerneed to thrive at S&P Global. Health & WellnessHealth care coverage designed for the mind and body. Continuous LearningAccess a wealth of resources to grow your career and learn valuable new skills. Invest in Your FutureSecure your financial future through competitive pay, retirement planning, a continuing education program with a company-matched student loan contribution, and financial wellness programs. Family Friendly PerksIts not just about you. S&P Global has perks for your partners and little ones, too, with some best-in class benefits for families. Beyond the BasicsFrom retail discounts to referral incentive awardssmall perks can make a big difference. For more information on benefits by country visithttps://spgbenefits.com/benefit-summaries Global Hiring and Opportunity at S&P Global: At S&P Global, we are committed to fostering a connected andengaged workplace where all individuals have access to opportunities based on their skills, experience, and contributions. Our hiring practices emphasize fairness, transparency, and merit, ensuring that we attract and retain top talent. By valuing different perspectives and promoting a culture of respect and collaboration, we drive innovation and power global markets. ----------------------------------------------------------- Equal Opportunity Employer S&P Global is an equal opportunity employer and all qualified candidates will receive consideration for employment without regard to race/ethnicity, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, marital status, military veteran status, unemployment status, or any other status protected by law. Only electronic job submissions will be considered for employment. If you need an accommodation during the application process due to a disability, please send an email to EEO.Compliance@spglobal.com and your request will be forwarded to the appropriate person. US Candidates Only The EEO is the Law Poster http://www.dol.gov/ofccp/regs/compliance/posters/pdf/eeopost.pdf describes discrimination protections under federal law. Pay Transparency Nondiscrimination Provision - https://www.dol.gov/sites/dolgov/files/ofccp/pdf/pay-transp_%20English_formattedESQA508c.pdf ----------------------------------------------------------- 20 - Professional (EEO-2 Job Categories-United States of America), IFTECH202.1 - Middle Professional Tier I (EEO Job Group)

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational 2+ years of experience with a Bachelors/ Masters degree in Electrical engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FVExperience in Logic design/micro-architecture/RTL coding is a must.Must have hands on experience with design and integration of complex multi clock domain blocksExperience in Verilog/System-Verilog is a must.Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architectureHands on experience in Multi Clock designs, Asynchronous interface is a must.Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.Work closely with the Design verification and validation teams for pre/post Silicon debugHands on experience in Low power design is preferableExperience in Synthesis / Understanding of timing concepts for ASIC is must Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Join Qualcomms cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). You will work on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. A strong understanding of on-chip buses and bridges is essential to ensure seamless integration and performance across subsystems. Key Responsibilities Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling. Perform power-aware verification using UPF/CPF and validate low-power design intent. Execute performance verification to ensure bandwidth, latency, and throughput targets are met. Preferred Skills & Experience 2"“15 years of experience in digital design and verification. Deep understanding of bus protocols and bridge logic, including hands-on experience with AXI, AHB, and APB. Experience with CPU subsystem verification and performance modeling. Familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be) is a plus. Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python). Experience with power-aware verification methodologies and tools (e.g., UPF, CPF). Familiarity with performance verification techniques and metrics. Exposure to tools like Clearcase/Perforce and simulation/debug environments. Strong analytical, debugging, and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Bachelors or Masters degree in Electrical/Electronics Engineering, Computer Science, or related field. Relevant experience in hardware design and verification.