2736 Verilog Jobs - Page 11

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 8+/6+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills. Who You'll Work With Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world! We Are Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!

5 - 7 Years 1 Opening Noida Role description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes: Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures of Outcomes: Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected: Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely delivery: Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills development: Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work: Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity: Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples: Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples: Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments: Responsibility- Primary responsibility includes I/O, Macro Characterization, EDA View generation (Functional, Electrical and Physical) & Full package validation. He/she needs to be in constant contact with IP design experts to understand the IP design (schematic, Layout) & IP specification (more electrical characteristics and functional aspect). Must have skills: • Excellent understanding of digital design concepts and CMOS fundamentals. • Ability to quickly comprehend the functional and electrical specifications of custom/full custom IPs. • Proficient in IO/Standard cells/Memory characterization flow using industry-standard tools such as Kronos, Liberate, and Silicon Smart. • Strong understanding of various formats of liberty files, including NLDM, CCS, and LVF. • Skilled in custom layout and schematic design/updates. • Experienced in IP physical model generation (LEF, sign-off GDS, CDL) and conducting validation checks (DRC, LVS, ERC) with debugging skills. • Proficient in behavioral modeling using Verilog/SystemVerilog and testbench writing. • Experience in IBIS (Input/Output Buffer Information Specification) modeling is a plus. • Excellent team player who is disciplined, adaptable, and possesses strong communication skills. Qualification & Experience • B. Tech / M. Tech – Electronics/VLSI Engineering • 3 to 7 years of professional experience in EDA/CAD View generation domain. • Prior ST experience even as intern is preferred. Skills CAD Design engineer,Standard Cell,Cmos About UST UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join the Engineering Group, specifically the Hardware Engineering team. In this role, you will be responsible for developing micro-architecture and RTL design for security-related Cores, focusing on block level design. Your tasks will include enabling software teams to utilize hardware blocks efficiently and running ASIC development tools such as Lint and CDC. It will be crucial for you to report progress and communicate effectively against set expectations. As a qualified candidate, you should hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, with a minimum of 5 years of Hardware Engineering experience. Additionally, having 5 to 10 years of work experience in ASIC/SoC Design is preferred. Proficiency in RTL design using Verilog/System Verilog and knowledge of cryptography concepts like public/private key, hash functions, encryption/signatures algorithms (such as AES, SHA, GMAC, etc.) will be beneficial for this role. Experience in Root of Trust, HW crypto accelerators, defining HW/FW interfaces, Linting, CDC, LEC, and database management flows with tools like Clearcase/Clearquest will be advantageous. Strong programming skills in Verilog, C/C++, Python, and Perl are essential. Excellent oral and written communication skills, proactive attitude, creativity, curiosity, motivation to learn and contribute, and good collaboration skills are also desired qualities. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities throughout the application/hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. The company expects its employees to comply with all relevant policies and procedures, including those regarding the protection of confidential information. If you are a staffing or recruiting agency, please note that Qualcomm's Careers Site is exclusively for individuals seeking employment directly with Qualcomm. Unsolicited submissions from agencies will not be accepted. For more information about this Hardware Engineering position, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a skilled ASIC IP Cores Design Engineer to join their Hardware Engineering team. As a part of this role, you will be expected to work as a strong designer on peripheral IPs, providing design and microarchitecture solutions independently. Additionally, you will play a key role in guiding and mentoring junior team members and collaborating with external teams to address cross-team dependencies. Taking complete ownership of projects and driving them forward will be a significant part of your responsibilities. The ability to provide schedule estimates will be advantageous, along with prior experience in people management. To excel in this role, you should possess 3-6 years of work experience in ASIC IP cores design, with a Bachelor's degree in Electrical Engineering being required and a Master's degree being preferred. Knowledge of AMBA protocols such as AXI, AHB, and APB, as well as familiarity with SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and Ethernet, is highly desirable. Working closely with SoC verification and validation teams for pre and post-silicon debug will be part of your responsibilities. Proficiency in low power design, multi-clock designs, and asynchronous interfaces is a must. Experience in using ASIC development tools like Lint, CDC, Design Compiler, and Primetime is essential, along with an understanding of constraint development and timing closure. Proficiency in Synthesis and timing concepts will be an added advantage. You should have strong microarchitecting skills in RTL design from high-level design specifications. Excellent problem-solving abilities, effective communication, and teamwork skills are key requirements for this role. Being self-driven and capable of working with minimal supervision is crucial. Proficiency in System Verilog, Verilog, C/C++, Perl, and Python will be beneficial. The ability to lead a small design team will also be an advantage. A minimum qualification of a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 2+ years of Hardware Engineering experience, a Master's degree with 1+ year of relevant experience, or a PhD in a related field is required. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm for support. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to security and confidentiality. This is an exciting opportunity for a skilled engineer to join a dynamic team at Qualcomm. If you meet the qualifications and are excited about the prospect of contributing to cutting-edge projects, we encourage you to apply.,

You will be responsible for demonstrating expertise in RTL Coding using Verilog, System Verilog, or VHDL. Your role will involve a strong understanding of FPGA flow, Logic design, and Digital design. It is essential to have knowledge in FPGA architecture and proficiency in Tcl and Python scripting. You will be conducting Vivado testing of synthesis tool and other stages. This position does not entail Silicon RTL development or any HW flow or testing. Your communication skills are crucial, as you will be expected to communicate technical information in an organized and understandable manner. A customer-oriented approach is necessary, along with a demonstrated concern and willingness to assist customers. Good organizational skills, multitasking abilities, prioritization, and activity tracking are essential. Exceptional oral and written communication skills are also required. TekWissen Group is committed to equal employment opportunities and supports workforce diversity.,

As an FPGA Design Engineer, you will be responsible for designing, developing, and testing FPGA-based prototypes for advanced telecommunications systems. Your expertise will play a crucial role in accelerating our product development cycles and ensuring the reliability and performance of our solutions. Key Responsibilities: Design and develop FPGA-based prototypes for telecommunications systems. Collaborate with cross-functional teams to define system requirements and specifications. Implement and optimize FPGA designs using VHDL/Verilog or other hardware description languages. Perform simulation, verification, and debugging of FPGA designs. Conduct performance analysis and optimize FPGA implementations for speed, power, and area. Integrate FPGA prototypes with other system components and perform system-level testing. Document design processes, test plans, and results. Stay updated with the latest advancements in FPGA technology and telecommunications standards. Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience in FPGA design and prototyping, preferably in the telecommunications domain. Proficiency in VHDL, Verilog, and other hardware description languages. Experience with FPGA design tools such as Xilinx Vivado, Altera Quartus, or similar. Strong understanding of digital signal processing (DSP) and telecommunications protocols. Knowledge of high-speed serial interfaces (e.g., PCIe, Ethernet). Familiarity with system-level integration and testing. Excellent problem-solving and debugging skills. Strong communication and teamwork abilities. Preferred Skills: Experience with software-defined radio (SDR) or related technologies. Knowledge of wireless communication standards (e.g., 4G, 5G). Familiarity with embedded systems and microcontroller programming. Experience with scripting languages such as Python or TCL for automation. Join Us for: Opportunity to work on cutting-edge telecommunications technologies. Collaborative and innovative work environment. Competitive salary and benefits package. Professional growth and development opportunities.,

You are invited to join Evon Technologies Pvt. Ltd., a team of over 450 technologists dedicated to providing software services and consultation to international clients. As a CMMI Level 3 company and recognized as the Top Mobile App Development Co. of 2021, we are currently engaged in various projects involving iOS, Android, Java, HTML, PHP, Ruby on Rails, Phone Gap, .Net, Angular, Node, React, Salesforce, PowerBI, and other cutting-edge technologies. Our company is expanding rapidly, and we are seeking individuals who are intelligent, dedicated, and poised to enhance our existing teams. We are currently seeking FPGA/RTL Developers who possess the following qualities: intelligence, pragmatism, self-motivation, and a willingness to learn and contribute to both organizational and personal advancement. This position is based in Dehradun and requires candidates who are available immediately. Qualifications for this role include a minimum of 3 years of experience in software development using FPGA, expertise in physical layer signal processing, proficiency in Verilog/VHDL, and hands-on experience with Xilinx FPGA (vivado). Additionally, candidates should have experience in DO-254 based development and documentation. The ideal candidate will have a background in Design Engineering, Electrical Engineering, or Product Design, possess skills in Computer-Aided Design (CAD), demonstrate strong analytical and problem-solving abilities, be knowledgeable in FPGA and RTL design methodologies, and hold a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. If you meet these qualifications and are interested in this opportunity, please email your resume to ethi.sharma@evontech.com.,

Are you looking for a unique opportunity to be a part of something great Want to join a 20,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchips nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and its won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting. Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results. FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results. Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. Be an effective contributor in a cross-functional team-oriented environment. Write high-quality code in Verilog, VHDL, and C code for embedded processors. Maintain existing code. Learn new system designs and validation methodologies. Understand FPGA architectures. Be conversant with on-chip debug tool. Requirements/Qualifications: - Excellent verbal and written communication skills in English - 5+ Years experience in Design with RTL coding in Verilog and VHDL and Verification of RTL - Possess an in-depth understanding of hardware architectures, system-level IC design implementation, knowledge of how to create end-use scenarios - Optimizing code for FPGA architectures - Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools - Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE - Working knowledge of embedded software C/C++ is also a plus - Strong technical background in FPGA prototype emulation, and debug - Strong technical background in silicon validation, failure analysis, and debug - Excellent Board level debug capabilities in a lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal - Design with RTL coding in Verilog and VHDL is a must - Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools - Hands-on systems level design and debug experience with at least two of the following high-speed serial communications protocols: PCIe Gen1/2/3, Interlaken (10.3125 Gbps), CPRI (614.4Mbps - 12.672 Gbps), SGMII or QSGMII, XAUI or HiGig/+/II, 10GBASE-R/-KR, Serial Rapid IO Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.,

As a Lead Product Validation Engineer at Cadence in Noida, you will have the opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and make a significant impact. Cadence, a pivotal leader in electronic design, leverages over 30 years of computational software expertise to deliver software, hardware, and IP that bring design concepts to life. Our customers are the world's most innovative companies, driving exceptional electronic products across various market applications. At Cadence, we prioritize our employees" well-being by offering employee-friendly policies that focus on physical and mental health, career development, learning opportunities, and celebrating success tailored to individual needs. Our unique One Cadence - One Team culture fosters collaboration within and across teams to ensure customer success. You will be part of a diverse team of passionate and talented individuals dedicated to exceeding expectations for customers, communities, and each other every day. Your responsibilities as a Lead Product Validation Engineer include being an Electrical, Electronics, or Computer Science Engineer with a solid understanding of HDLs like Verilog and/or VHDL. You should have experience in simulation/emulation using these languages and a good working knowledge of EDA tools (Cadence/Other) to debug design/verification issues. The role requires experience in process automation with scripting, familiarity with SystemVerilog, C++, UVM, and Functional Verification of complex digital systems like SoC Verification using SystemVerilog. Additionally, knowledge of protocols such as PCIe, USB3/4, and DP is advantageous. The ideal candidate should hold a B. Tech or M. Tech/B.E./M.E. with 3-6 years of relevant experience. Strong written, verbal, and presentation skills are essential, along with the ability to establish close working relationships with customers and management. You should have a knack for exploring unconventional solutions to get the job done and work effectively across functions and geographies while maintaining integrity. Join Cadence in solving challenges that others can't, and be a part of work that truly matters.,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is seeking highly motivated and talented professionals to join their R&D center in Bengaluru. Eridu AI is a Silicon Valley-based hardware startup specializing in infrastructure solutions that enhance the performance of large-scale AI models. The company has introduced innovative advancements in semiconductors, software, and systems to address system-level bottlenecks, maximize GPU utilization, reduce costs, and enhance data center efficiency, which have been recognized by leading hyperscalers. Led by a team of experienced Silicon Valley executives and engineers, including serial entrepreneur Drew Perkins, Eridu AI is at the forefront of developing cutting-edge technologies. They are currently looking for experienced RTL designers to contribute to defining and implementing their industry-leading Networking ASICs. If you are a self-driven individual passionate about solving real-world problems, this is a unique opportunity to influence the future of AI Networking. As part of the Design Group, you will play a key role in defining, specifying, architecting, executing, and productizing state-of-the-art Networking chips. Your responsibilities will include working on microarchitecture, design implementation, testing, performance optimization, protocol support, troubleshooting, and debugging related to high-speed networking ASICs. Additionally, you will collaborate with cross-functional teams to ensure the functionality and reliability of the designs. To be considered for this role, you should have a ME/BE degree with a minimum of 8-15 years of experience, hands-on knowledge of SystemVerilog and Verilog, a solid understanding of ASIC design methodologies, expertise in designing and optimizing scheduling and QoS mechanisms, familiarity with Ethernet and IP protocols, strong analytical and problem-solving skills, and excellent communication abilities. Joining Eridu AI will offer you the chance to work with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary will be determined based on various factors, including skills, experience, qualifications, and market trends. For more information about the company, please visit eridu.ai.,

As an RTL Engineering Lead at Google, you will play a vital role in driving innovation and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will be instrumental in shaping the future of hardware experiences that cater to millions of users worldwide. By leveraging your expertise, you will enhance performance, efficiency, and integration in the next generation of Google products. With a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience, along with 6 years of hands-on experience in micro-architecture and coding, particularly in memory compression, interconnects, coherence, cache, Dynamic Random-Access Memory controller, and Physical Layer Device, you are well-equipped to excel in this role. Proficiency in Verilog or SystemVerilog language is a must to thrive in this dynamic environment. Ideally, you possess experience in high-performance design, multi-power domains with complex clocking, and have a proven track record of delivering successful SoCs. Your expertise in microarchitecture design and system design will be pivotal in developing highly optimized IPs with excellent Power, Performance, and Area (PPA) metrics. Familiarity with chip design flow and quality checks at the front end, including Lint, CDC/RDC, Synthesis, and Line Echo Cancellation, will further enhance your capabilities. In this role, you will lead a team of RTL engineers, overseeing IP development plan tasks, conducting code and design reviews, and driving the development of complex features within the IP. Collaboration with the architecture team is essential to strategize microarchitecture and coding implementations that align with quality, schedule, and PPA goals. Additionally, you will work closely with cross-functional teams, including Verification, Design for Test, Physical Design, and Software teams, to make informed design decisions and ensure project progress is effectively communicated throughout the development lifecycle. Join our diverse team of passionate individuals who are committed to pushing boundaries and creating innovative solutions that enhance the lives of people globally. Together, we aim to make technology faster, seamless, and more powerful, ultimately realizing Google's mission of organizing the world's information and making it universally accessible and useful.,

As an experienced HDL design/verification engineer at Lattice Semiconductors, you will play a pivotal role in designing, developing, and enhancing simulation capabilities within Lattice Radiant, the official FPGA design tool. Working closely with hardware developers and QA teams, you will be responsible for enabling and supporting simulation workflows for Verilog, VHDL, and SystemVerilog across various Lattice FPGA families. Your key responsibilities will include diagnosing and resolving simulation issues, validating and testing simulation features, contributing to automation scripts and testbench generation tools, as well as maintaining simulation documentation, troubleshooting guides, and user tutorials. You will have the opportunity to work on cutting-edge technologies and have a direct impact on the evolution of FPGA development tools and methodology. To excel in this role, you must possess a Bachelor's or Master's degree in Electronics Engineering or a related field, along with solid experience in hardware description languages (HDLs) and simulation tools such as Modelsim and Synopsis VCS. A strong understanding of HDL simulation concepts, EDA tool development, FPGA architectures, and configuration flows is essential. Industrial experience in a similar field for more than 5 years is a requirement. Preferred skills for this role include strong analysis and debugging capabilities, as well as excellent communication and cross-disciplinary collaboration skills. In return, Lattice Semiconductors offers competitive compensation, comprehensive benefits, a highly collaborative and intellectually driven team environment, and supportive cross-geo team environment with technical mentorship. If you thrive in a fast-paced, results-oriented environment and are looking to contribute to a dynamic team, Lattice Semiconductors may be the perfect fit for you.,

Job Titles: Senior Staff ASIC Verification Engineer- Pune Location We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and passionate ASIC Digital Verification engineer, ready to take on technical leadership in a dynamic, high-impact environment. With a proven track record of developing and validating complex UVM verification environments, you thrive in collaborative settings and enjoy mentoring others. You bring a deep understanding of digital verification flows, simulation, and coverage analysis, and you excel at identifying and solving challenging design problems. Your experience spans 8-15+ years in ASIC verification, where you've consistently demonstrated your ability to architect, plan, and execute verification strategies. You’re comfortable multitasking between multiple projects and have a genuine desire to stay at the forefront of emerging technologies. You communicate effectively in both written and spoken English, and your organizational skills help ensure that projects are delivered on time and to the highest quality standards. You’re motivated by the opportunity to make a significant impact, not just through your own work, but by elevating the entire team around you. Your proactive approach to learning, problem-solving, and process improvement defines your professional ethos. What You’ll Be Doing: Identify verification environment requirements from specifications, design functionalities, and interfaces. Generate comprehensive verification test plans and maintain detailed documentation for verification environments and their usage. Define, develop, and verify advanced UVM (Universal Verification Methodology) environments for complex ASIC designs. Evaluate and exercise all aspects of the verification flow, including Verilog/SystemVerilog development, functional simulation, constraint development, behavioral modeling, and coverage metrics analysis (functional and code coverage). Collaborate closely with architects, designers, and the VIP team to ensure seamless integration and accomplishment of project goals. Identify design problems, propose corrective actions, and resolve inconsistencies in documented functionalities. Mentor and guide junior engineers, supporting them in debugging and solving complex verification problems. Support customer issues through issue reproduction and in-depth analysis, ensuring customer satisfaction. Drive continuous improvement of verification methodologies and execution efficiency within the team. Adhere to best practices, quality standards, and maintain a high level of test and verification rigor. The Impact You Will Have: Accelerate the delivery of robust, high-quality ASIC products by ensuring thorough and systematic verification. Enhance the team’s technical capabilities by sharing expertise and mentoring junior engineers. Directly contribute to Synopsys’ reputation for excellence in silicon design and verification solutions. Drive innovation in verification methodologies, raising the bar for future projects and industry standards. Improve customer satisfaction by providing expert support and resolving technical challenges efficiently. Facilitate cross-functional collaboration, fostering a culture of knowledge sharing and continuous learning. What You’ll Need: 8-15+ years of hands-on experience in ASIC digital verification, preferably in a lead or staff engineering capacity. Proficiency in Verilog, VHDL, and/or SystemVerilog languages, with a strong grasp of modern verification methodologies such as UVM. Experience in developing and debugging verification environments, including test planning, simulation, and coverage analysis. Familiarity with industry-standard scripting languages (BASH, TCSH, PERL, PYTHON, TCL) for automation and workflow optimization. Excellent written and spoken English communication skills, with the ability to document and present technical concepts clearly. Strong organizational skills, with experience managing multiple priorities and delivering high-quality results under tight deadlines. Who You Are: Innovative and proactive, with a passion for continuous learning and embracing new technologies. Collaborative team player who thrives in a diverse, multicultural environment. Analytical thinker with exceptional problem-solving and troubleshooting abilities. Effective mentor and leader, capable of guiding and inspiring junior engineers. Detail-oriented and process-driven, committed to delivering excellence in every project. Resilient and adaptable, able to multitask and manage shifting priorities in a fast-paced setting. The Team You’ll Be A Part Of: You will join a world-class team of verification engineers dedicated to delivering high-performance, reliable ASIC solutions. Our team values technical excellence, innovation, and collaboration. We work closely with architects, designers, and validation teams to ensure robust product delivery. As a senior member of the team, you will have the opportunity to influence verification strategies, lead technical initiatives, and mentor the next generation of engineering talent at Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Key skills with hand on :Design Verification, System Verilog ,SOC, SV -UVM, Testplan, Test bench, VCS, Verdi, Cadence, Simvision, jasper Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: • 6+ years of hands-on DV experience in SystemVerilog/UVM. • Must be able to own and drive the verification of a block / subsystem or a SOC. • Should have a track record of leading a team of engineers. • Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. • Experience in Tesplan and Testbench development, • Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. • Should be good with debugging and exposed to all aspects of verification flow including Gatesims • Must have extensive experience in verification of one or more of the following: o PCI Express or UCIe, CXL or NVMe o AXI, ACE or CHI o Ethernet, RoCE or RDMA o DDR or LPDDR or HBM o ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages o Power Aware Simulations using UPF • Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. • Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase. • Experience in SVA and formal verification is desirable (not a must) • Script development using Python, Perl or TCL is desirable (not a must)

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Work Experience 1. Good fundamentals in analog and mixed signal circuit concepts and topologies. 2. Experience working with mixed signal verification environment, simulation, and regression tools such as Cadence Virutuoso, Spectre, xCelium, Incisive, vManager, IMC 3. Ability to read analog schematics and extract related main functionality. 4. Familiar with Verilog based RTL coding and ASIC design methodology. 5. Experience in System Verilog for advanced verification methodologies such as assertions, constrained randomization, metric driven, and UVM. 6. Familiar with behavioral modelling of analog blocks using System Verilog (RNM) and VerilogAMS. 7. Experience in modelling analog & mixed signal blocks. 8. Some knowledge of UNIX shell scripting, Perl, Python and TCL scripting.

As FPGA Design Lead, your role will be to manage and lead design engineers to implement complex FPGA IPs and FPGA-based digital designs. You should be able to understanding the project requirements and define architecture/Micro architecture with proper documentation.You will be guiding the team for system development Job Responsibilities : ➢ You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines) ➢ Understand the customer requirements and product definition ➢ Define architecture and detailed design spec based on requirements and various trade-offs ➢ Micro-architecture and coding of assigned module in VHDL/Verilog ➢ Write test bench for verifying design for complete scenario coverage ➢ Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement ➢ FPGA debugging and HW/SW integration Requirements: ● 6+ years of experience, including successful completion of FPGA based projects ● Coding experience in VHDL and/or Verilog is must ● Experience targeting Xilinx and/or Altera FPGAs required ● Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required ● Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor ● Implementation of designs with multiple clock domains is required ● Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed ● Experience in RTL implementation of DSP algorithms will be appreciated ● Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated Job Type: Full-time Pay: ₹450,000.00 - ₹580,000.00 per month Schedule: Day shift Ability to commute/relocate: Gurugram, Haryana: Reliably commute or willing to relocate with an employer-provided relocation package (Required) Experience: FPGA: 6 years (Required) Language: English (Required) Location: Gurugram, Haryana (Required)

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 3 -7 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: - Designing, developing, and troubleshooting core algorithms for compiler. - Collaborating with local and global teams to enhance runtime performance for verilog compiler. - Engaging in pure technical roles focused on software development and architecture. - Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions. The Impact You Will Have: - Driving technological innovation in chip design and verification. - Enhancing the performance and quality of simulation tools used globally. - Solving complex compiler optimizations problems to improve simulation performance. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: - Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: - Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Description The position involves design verification of next generation IP’s /SoC’s with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. Responsibilities: To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected Experience working on AMS Verification on multiple SOC’s or sub-systems Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites Developing and validating high-performance behavior models Verifying of block-level and chip-level functionality and performance Team player with good communication skills and previous experience in delivering solutions for a multi-national client Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. Ability to extract simulation results, capture in a document and present to the team for peer review Supporting silicon evaluation and comparing measurement results with simulations UVM and assertion knowledge would be an advantage Experience Level: 3-15 years in Industry , Work Location: Hyderabad , Bangalore. Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering Minimum Qualifications: Proficient in at least one of the following languages: Verilog, SystemVerilog, VerilogAMS. Strong understanding of analog circuits, digital design processes, and top-level integration. Basic knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a basic understanding of Python.

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments Responsibility- Primary responsibility includes I/O, Macro Characterization, EDA View generation (Functional, Electrical and Physical) & Full package validation. He/she needs to be in constant contact with IP design experts to understand the IP design (schematic, Layout) & IP specification (more electrical characteristics and functional aspect). Must have skills: Excellent understanding of digital design concepts and CMOS fundamentals. Ability to quickly comprehend the functional and electrical specifications of custom/full custom IPs. Proficient in IO/Standard cells/Memory characterization flow using industry-standard tools such as Kronos, Liberate, and Silicon Smart. Strong understanding of various formats of liberty files, including NLDM, CCS, and LVF. Skilled in custom layout and schematic design/updates. Experienced in IP physical model generation (LEF, sign-off GDS, CDL) and conducting validation checks (DRC, LVS, ERC) with debugging skills. Proficient in behavioral modeling using Verilog/SystemVerilog and testbench writing. Experience in IBIS (Input/Output Buffer Information Specification) modeling is a plus. Excellent team player who is disciplined, adaptable, and possesses strong communication skills. Qualification & Experience B. Tech / M. Tech – Electronics/VLSI Engineering 3 to 7 years of professional experience in EDA/CAD View generation domain. Prior ST experience even as intern is preferred. Skills CAD Design engineer,Standard Cell,Cmos

Key skills with hand on: ASIC,RTL Design, VLSI-SOC ,AMBA, Lint, CDC, Synopsys LintCDC/VerdiXcellium/Synopsys DC. Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: IP RTL design targeted for SOC, Static checks, some basic protocols Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks ( Lint, CDC ) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB ) Good understanding of timing concepts Knowledge of one or more of the interface protocols PCIe/DDR/Ethernet/I2C,UART/SPI Expertise in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills We are seeking an experienced HDL design/verification engineer to design, develop, and enhance the simulation capabilities within Lattice Radiant — Lattice Semiconductor’s official FPGA design tool. You’ll be part of the Lattice Software Radiant team working closely with the hardware developers and QA teams to support simulation flows, help validate new features and ensure seamless integration of simulation engines with Radiant’s toolchain. Key Responsibilities Enable and support simulation workflows for Verilog, VHDL, and SystemVerilog across various Lattice FPGA families Assist in diagnosing and resolving simulation issues reported by internal developers or users Validate and test simulation features, waveform viewers, and debug interfaces within Radiant Contribute to automation scripts and testbench generation tools Maintain simulation documentation, troubleshooting guides, and user tutorials Required Qualifications Bachelor’s or Master’s degree in Electronics Engineering, or related field Solid experience with hardware description languages (HDLs) and simulation tools (e.g., Modelsim, Synopsis VCS) Solid understanding of HDL simulation concepts: elaboration, scheduling, waveform generation Solid experience in EDA tool development or FPGA simulation frameworks Familiarity with Lattice Radiant Software, FPGA architectures, and configuration flows Industrial experience in similar field for > 5 years. Preferred Skills Strong analysis and debugging capabilities Excellent communication and cross-disciplinary collaboration skills What We Offer Direct impact on the evolution of FPGA development tools and methodology Competitive compensation and comprehensive benefits A highly collaborative and intellectually driven team environment Supportive cross-geo team environment and technical mentorship

As FPGA Design Lead, your role will be to manage and lead design engineers to implement complex FPGA IPs and FPGA-based digital designs. You should be able to understanding the project requirements and define architecture/Micro architecture with proper documentation.You will be guiding the team for system development Job Responsibilities : ➢ You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines) ➢ Understand the customer requirements and product definition ➢ Define architecture and detailed design spec based on requirements and various trade-offs ➢ Micro-architecture and coding of assigned module in VHDL/Verilog ➢ Write test bench for verifying design for complete scenario coverage ➢ Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement ➢ FPGA debugging and HW/SW integration Requirements: ● 6+ years of experience, including successful completion of FPGA based projects ● Coding experience in VHDL and/or Verilog is must ● Experience targeting Xilinx and/or Altera FPGAs required ● Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required ● Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor ● Implementation of designs with multiple clock domains is required ● Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed ● Experience in RTL implementation of DSP algorithms will be appreciated ● Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated Job Type: Full-time Pay: ₹450,000.00 - ₹580,000.00 per month Schedule: Day shift Ability to commute/relocate: Gurugram, Haryana: Reliably commute or willing to relocate with an employer-provided relocation package (Required) Experience: FPGA: 6 years (Required) Language: English (Required) Location: Gurugram, Haryana (Required)

As an FPGA Designer in the Research and Development department, you will play a crucial role in defining and developing intricate FPGA designs for AWG & Digitizer products. Working in a dynamic and collaborative environment, you will closely collaborate with the R&D Project Manager, Product Architects, Solution Teams, Software Qualification, and Software Engineers to enhance existing products and introduce new offerings. Your ability to work effectively within a team, including other design teams based in the US & Europe, is essential for success in this role. Key Requirements: - A Bachelor's or Master's degree in Electrical / Electronic Engineering. - 8-10 years of hands-on experience in FPGA development with proficiency in Altera and Xilinx technologies. - Proficiency in RTL languages such as VHDL and Verilog. - Familiarity with Xilinx FPGA Tools Design Flow, including Vivado and Chipscope. - Experience in achieving timing closure for complex designs. - Proficiency in Functional Simulation tools like Synopsys, Mentor, Cadence, or Vivado simulator. - Ability to develop self-checking Simulation environments involving test benches, automation scripts, and test case creation. - Quick adaptability to new technologies and product segments. - Strong written communication skills for creating various technical documents. - Self-motivated, organized, and accountable individual. - Excellent team player with responsive communication skills. Preferred Skills: - Experience in high data throughput real-time processing (~ 1GSPS), PCIe, DDR memories, FSM, etc. - Familiarity with Test & Measurement lab equipment. - Knowledge of C/C++ programming languages. In this role, your expertise and dedication will contribute significantly to the advancement and innovation of FPGA designs for cutting-edge products.,