Senior ASIC RTL Designer

Role Overview: You will be responsible for designing and developing synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Additionally, you will create micro-architecture specs and ensure that designs meet performance, power, and area targets. You will own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT readiness. Collaboration with verification teams for test planning, debugging, and coverage closure will also be a key part of your role. Furthermore, you will integrate IPs into top-level SoC and resolve timing and functionality issues. Finally, you will support emulation, FPGA prototyping, and silicon bring-up activities with cross-functional teams. Key Responsibilities: - Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks - Create micro-architecture specs and ensure designs meet performance, power, and area targets - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT readiness - Collaborate with verification teams for test planning, debugging, and coverage closure - Integrate IPs into top-level SoC and resolve timing and functionality issues - Support emulation, FPGA prototyping, and silicon bring-up activities with cross-functional teams Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field - 6+ years of experience in ASIC RTL design - Proficiency in Verilog/SystemVerilog - Strong understanding of micro-architectural concepts - Experience in synthesis, timing analysis, and DFT - Excellent communication and collaboration skills Note: No additional details of the company were provided in the job description.,