Functional Verification Engineer

0 years

0 Lacs

Posted:1 day ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Why Luxoft?


  • Work–Life Balance

    with flexible work hours (agreed with your manager).
  • Multiple working modes:

    Physical, Flexible, Virtual, and Onsite.
  • Cab facilities

    for employees.
  • Free gym access

    + free sports equipment and sports zones.
  • Corporate sports events

    and well-being programs.
  • LuxGood activities:

    motivational talks, games, wellness content, community events.
  • Employee Assistance Program:

    counselling, self-help tools, chats, assessments.
  • Bike parking

    available at all locations.
  • Meal/Food coupon card

    with tax benefits.
  • Attractive shopping discounts

    with 110,000+ partners.


Leave Benefits

  • 25 annual leave days

    +

    12 public holidays

    .
  • Sick leave:

    13 days/year.
  • Marriage leave:

    5 days.
  • Compassionate leave:

    5 days.
  • Maternity leave:

    6 months.
  • Paternity leave:

    5 days.
  • Medical leave:

    up to 60 days/year.


Insurance & Support

  • Comprehensive

    medical insurance

    for employee, spouse, children, and parents.
  • Top-up insurance options

    available.
  • Klay crèche facility

    for female employees with childcare support.


Financial Benefits

  • Cash advance program

    for emergencies (0% interest).
  • NPS

    &

    Voluntary Provident Fund

    for long-term savings.
  • Company car lease scheme

    (after 12 months).


About the project:

We are seeking an experienced Functional Verification Engineer with strong expertise in System Verilog/UVM to develop and maintain verification environments for block-level and IP-level designs. The ideal candidate will be proactive, self-driven, and capable of managing deliverables independently.


Responsibilities:

- Develop and maintain block-level verification environments and testbenches using SystemVerilog/UVM.

- Create and execute verification plans (VPlans), run regressions, and drive coverage closure.

- Implement and verify designs using real number modeling (RNM) for mixed-signal interfaces.

- Perform netlist and gate-level simulations (GLS) to validate post-synthesis and post-layout functionality.

- Debug functional and testbench issues, ensuring high-quality, reusable verification components.


Skills Description:

* 5-10y exp

* Develop and maintain block-level testbenches using System Verilog/UVM.

* Create and execute verification plans (Vplan), run regressions, and achieve coverage closure.

* Work on testbenches with real number modeling.

* Perform netlist and gate-level simulations.

* Hands-on coding in SystemVerilog/UVM.


Nice-to-have skills:

* Experience with block/IP-level verification; subsystem or SoC-level experience is a plus.

* Soft Skills: Strong communication, ability to work independently and meet schedules.


Languages:

English: C2 Proficient


Luxoft is committed to fostering a diverse and inclusive workplace.

We show fairness to all throughout our talent acquisition and management process.

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