1643 Verilog Jobs - Page 40

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What you’ll be doing: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. #LI-Hybrid What we need to see: B.Tech./ M.Tech or equivalent experience 2+ years of relevant experience Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd: Excellent knowledge of PCIE protocol - Gen3 and above Good understanding of the system level architecture of PCIE/CXL-based designs Perl, Python or similar scripting and SW programming language experience Good debugging and analytical skills Good interpersonal skills & dream to work as a great teammate With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. You will be required to undertake complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes: Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics SubSystem/SOC verification covering functional and firmware scenarios in RTL and GLS. DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs. Develop and maintain comprehensive verification environments using UVM Active collaboration with cross functional teams - Architecture, RTL, PD, DFT, Systems, Analog, FW and Application teams to ensure comprehensive verification of specific IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities Mentor junior verification engineers and review their work. Establish verification methodologies and best practices QUALIFICATIONS Minimum requirements: Minimum of 3-4 years of experience in Digital IP Sub-system/SOC DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Experience in one or many of the following: C based Digital DV, scripting (Python/Perl/Shell) knowledge, UVM/System Verilog, AMS/GLS/CPF/UPF based verification, Post silicon verification etc Preferred qualifications: Strong in digital design fundamentals, computer organization & architectures and bus protocols. A good understanding of analog functionality and exposure to analog IC design methods. Ability to solve problems using a systematic approach Excellent debugging skills with Verilog/VHDL designs Work experience on C based environment with ARM/DSP processor-based systems including power aware simulations is a plus. Experience in Motor control/ BLDC motor driver devices including commutation, sensorless control and feedback systems are an added advantage Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Effective communication skills to interact seamlessly with all stakeholders Ability to quickly ramp on new systems and processes Ability to work in teams and collaborate effectively with people in different functions Ability to take the initiative and drive for results Strong time management skills that enable on-time project delivery ABOUT US Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com. Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. JOB INFO Job Identification 25001296 Job Category Engineering - Product Dev Posting Date 06/05/2025, 01:11 PM Apply Before 06/06/2025, 01:30 PM Degree Level Bachelor's Degree Locations BANG Bagmane Tech Park, Bangalore, 560093, IN ECL/GTC Required Yes

Mirafra is hiring!!! Hardware (HW) Verification Engineer Location: Hyderabad Experience: 5 to 10 Years Job Description: Mirafra Technologies is hiring experienced Hardware Verification Engineers to work on top-tier SoC verification projects. The ideal candidate will have strong UVM/SystemVerilog expertise and hands-on experience with FPGA and protocol-level testing. Responsibilities: Develop SV/UVM testbenches at Top/Sub-system/Block-levels Drive creation and execution of test plans and test specs Document verification phases: user guides, test reports, and execution logs Contribute to verification architecture and methodology development Required Skills: Strong programming skills in SystemVerilog and UVM Protocol verification experience: Ethernet, PCIe, SPI, I2C, USB Hands-on hardware testing experience using logic analyzers, traffic generators Exposure to FPGA verification and Xilinx tools Solid debugging skills at both device and board level Proficiency in scripting languages: Perl, Python, TCL Strong interpersonal, communication, and analytical skills Apply Now or send your resume to swarnamanjari@mirafra.com Note: This is a client-based selection process .

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very upbeat and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your Role We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to create new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards chipping into your success. We Are Not Looking for Superheroes, Just Super Minds! We’ve got quite a lot to offer. How about you? Required Experience We seek a graduate with at least 8+ years of relevant working experience with B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college. We value proficiency of C/C++, algorithm and data structures. Compiler Concepts and Optimizations. Experience with UNIX and / or LINUX platforms is vital. Basic Digital Electronics Concepts We value your knowledge of Verilog, System Verilog, VHDL Experience in parallel algorithms, job distribution. Understanding of ML/AI algorithms and their implementation in data-driven tasks Exposure to Simulation or Formal based verification methodologies would be a plus! The person should be self-motivated and can work independently. Should be able to guide others, towards project completion. Good problem solving and analytical skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability #DVT Show more Show less

Minimum qualifications: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field, or equivalent practical experience. 5 years of experience with ML/AI frameworks and libraries (e.g., TensorFlow, PyTorch, scikit-learn). Experience with hardware description languages (e.g., Verilog, SystemVerilog, VHDL). Experience with applying ML/AI techniques. Preferred qualifications: Experience with ML/AI applications in hardware design, verification and Low Power (e.g., formal verification with ML, coverage closure with ML). Experience with verification methodologies (UVM, OVM). Experience in data preprocessing and feature engineering, hardware architecture and microarchitecture. Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Excellent programming skills in Python or C++. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Research, design, and implement ML/AI algorithms techniques for various verification tasks, including test case generation, coverage analysis, bug prediction, and performance optimization. Develop and maintain tools and scripts for data collection, preprocessing, model training, and evaluation. Analyze large datasets of simulation results, logs, and other verification data to identify patterns and trends. Build and train ML models for various verification applications, such as anomaly detection, pattern recognition, and prediction. Evaluate model performance and iterate to improve accuracy and efficiency. Participate in verification planning and develop test plans that incorporate ML/AI-driven techniques. Execute verification tests and analyze results to identify bugs and coverage gaps. Develop and maintain verification tools and scripts to automate verification tasks. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Show more Show less

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in Design Verification. 4 years of experience in people management, developing employees. Experience constructing reusable verification components and environments using Universal Verification Methodology (UVM), System Verilog or similar. Experience in Portable Stimulus Standard (PSS), formal or emulation based SimXL methodologies. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. Experience in one or more of the following like Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), Peripheral Component Interconnect Express (PCIe), or Packet Processors. Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling. Experience with Formal verification techniques, System Verilog Assertions (SVA) and assertion-based verification. Experience building verification methodologies that span simulation, emulation and Field Programmable Gate Array (FPGA) prototypes. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead and manage verification activities for complex Slow-Slow (SS) or System on a Chip (SoC). Develop all aspects of logic verification infrastructure and methodology for complex mobile SoC Internet Protocol (IP) or SS blocks. Collaborate with design teams to ensure integration of verification methodology into the design process. Optimize and improve verification methodologies to increase efficiency and effectiveness. Collaborate with both external and internal Computer Aided Design (CAD) teams to develop new verification solutions that can improve the quality and efficiency. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle. Preferred Qualifications B.E/B.Tech/M.E/M.Tech in Electronics with 5+ year experience in verification domain. Strong fundamentals in digital ASIC verification Experience in IP/SS/SoC level verification of medium to high complexity design Familiarity with system level HW and SW Debug techniques and Verification requirements A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) Strong System Verilog/UVM based verification skills & Experience with Assertion & coverage-based verification methodology Experience w/ PSS or higher-level test construction languages is an added advantage Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Roles and Responsibilities Define verification architecture, develop test plans and build verification environment Work with design team to understand design intent and bring up verification plans and schedules Verify Subsystems and Full SoC using advanced verification methodologies Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard Develop test plan to verify all low power aspects across all modes of verification – RTL, PA-RTL, PA-GLS and Formal Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Assist in silicon bring-up, debug and bring-up activities Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075599 Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Develops high-quality, reliable, and efficient hardware designs for medical devices, including analog, digital, and mixed-signal circuits. Collaborates with cross-functional teams to ensure successful integration of designs into medical products. Participates in the development of new products, from concept to production. Ensures successful integration of electrical design with mechanical and software elements of the system. Provides technical guidance and mentorship to junior engineers. Develops, modifies, and approves electrical design documentation, specifications, and drawings. Supervises/coordinates an engineer and/or technicians on assigned work. Defines design requirements and hardware specifications based on customer or user requirements. Contributes to the development and documentation of electronic system architectures. Conducts design reviews, trade-off analyses, and risk assessments to ensure the optimal design solution is selected for each project. Leads the creation of designs of electronic circuit schematics for microcontroller-based systems and microprocessor-based systems, meeting performance objectives. Analyzes circuits using calculation and simulation methods to assess performance limits, effects of environmental and load stress, and timing interfaces to ensure consistent performance in safety-critical applications. Stays up to date with industry trends, emerging technologies, and regulatory requirements to maintain a competitive edge. Contributes to the development of design verification and validation plans, as well as executing tests to ensure design compliance with specifications. Defines appropriate test methods to verify designs meet their performance requirements. Completes deliverables related to design of systems and sub-systems of the overall electrical architecture. Collaborate with suppliers and external partners to source components and ensure component reliability and availability. Participates in the transfer of design knowledge and intellectual property to manufacturing teams to ensure successful production ramp-up. Contributes to the continuous improvement of design processes, tools, and methodologies to improve efficiency and quality. Directs the layout of circuit assemblies to meet emissions and immunity performance requirements and design for manufacturability guidelines. Executes protocols and testing required to validate the safety and effectiveness of the design(s). Leads the troubleshooting and problem-solving efforts related to electrical aspects of devices and associated systems. Creates and communicates design/test plans, tasks, deliverables, and status. Manages time and resources to meet committed schedule milestones.) Qualifications A Bachelor's or Master's degree in Electrical or Electronics Engineering or a related field is required, with a minimum of 11 years of experience in electro-mechanical medical device product design, with knowledge of infusion pumps medical devices being an added advantage. A strong foundation in digital electronics, including logic design, digital circuits, and computer architecture. Proficiency in digital logic design, timing analysis, AC & DC analysis, and familiarity with simulation tools such as VHDL, Verilog, and Cadence is an added advantage. Strong knowledge of digital circuit design, digital system architecture, and design methodologies using microcontrollers, microprocessors, System on Module (SOM), CPLD, FPGAs, and ASICs. Knowledge of digital components, such as logic gates, flip-flops, memory technologies (such as SRAM, DRAM, and flash memory), digital signal processing, and communication protocols (such as I2C, SPI, USB, and Ethernet). Familiarity with Ethernet physical layers, such as RJ45, twisted pair, and fiber optics, and networking hardware, such as switches, routers, and hubs. Knowledge of Wi-Fi networking hardware, such as access points, routers, and client devices, and understanding of Wi-Fi network topologies, Wi-Fi testing and troubleshooting tools, and methodologies. Understanding of Wi-Fi power management and quality of service (QoS) mechanisms. Familiarity with Ethernet network management tools, such as SNMP and NetFlow, and Wi-Fi protocols, including TCP/IP, UDP, and ICMP. Understanding of Ethernet power over data (PoE) and power over Ethernet plus (PoE+) technologies. Knowledge of industry standards and regulations, such as TIA/EIA and ETSI, to ensure compliance with network performance and safety requirements. Familiarity with PCB layout and design for manufacturability (DFM) principles. Knowledge and experience using CAD systems for printed circuit board schematic design and layout (preferably Altium Designer). Understanding of signal integrity and power integrity concepts to ensure reliable performance of circuits. Experience with measurement and testing equipment to verify circuit performance. Experience with design automation tools, such as LabVIEW, Cadence Virtuoso, AWR Design Environment, or MATLAB. Strong problem-solving skills and the ability to work independently and collaboratively. Excellent communication skills, both written and verbal, with the ability to effectively communicate complex technical concepts to non-technical stakeholders. Strong organizational skills and the ability to manage multiple projects simultaneously. Experience with regulatory requirements, such as FDA 510(k) and IEC 60601, is a plus. Familiarity with agile development methodologies and the ability to work in a fast-paced, dynamic environment and adapt to changing priorities.

Computer Hardware Engineer Responsibilities & Duties Design, develop, and test computer hardware components and systems Collaborate with cross-functional teams to integrate hardware with software systems Perform thorough testing and debugging of hardware components Analyze and resolve technical issues related to hardware components Develop technical documentation for hardware designs and systems Stay up-to-date with industry trends and advancements in computer hardware engineering Provide technical support to customers and other stakeholders as needed Computer Hardware Engineer Qualifications & Skills Masters degree or higher in Computer Engineering, Electrical Engineering, or related field Experience with FPGA, PLC, or embedded systems development Proficiency in hardware description languages (HDLs) such as VHDL or Verilog Knowledge of circuit design and simulation tools Experience in high-speed digital design Familiarity with hardware security measures Strong problem-solving and analytical skills Excellent communication and teamwork abilities Experience with debugging and testing hardware Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or related field Expertise in hardware design, development, and testing In-depth knowledge of computer systems and components, including processors, memory, and peripherals Experience with schematic capture and PCB layout tools, such as Altium Designer or Eagle PCB Excellent problem-solving and analytical skills Strong verbal and written communication skills, including technical writing

Role & responsibilities "You will be closely working with Architecture Team, SOC Design Team, Product Design, Software Teams; Understand the requirement, enhancements required etc; create a realistic schedule and resource plan You will completely own the IP Design; preparing the micro-architecture, detailed design document, implement design using RTL coding techniques, performing reviews and ensuring all quality criteria are met Work with verification team on reviewing the verification test plan to ensure design features are verified correctly, issue debug, coverage analysis etc Provide support to SOC Integration, Physical Design, Software, Product Engineering team on pre & post silicon activities on need basis" Preferred candidate profile - Min 7 years full time experience in IP design, Detailed understanding of SOC Design - Good understanding and Hands on experience in interconnect designs, multi-clock designs, SoC BUS architecture and NOC concept; - Experience in performance and latency tuning will be an add-on - Proficiency in IP Design using Verilog, System Verilog hardware logic design language - Sound knowledge of AMBA protocols like APB/AHB/AXI/ACE/ACE-Lite -Self-driven, Strong problem solving, root causing and debugging skill -Experience in creating documents such as micro-architecture, hardware design document, verification request etc -Work collaboratively with other members of the IP Team, SOC Team, cross-functional teams across various geographies - Good written and verbal communication skills

Responsibilities: The candidate would be part of the VIP group responsible for development of Verification IPs. Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification. The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment. This is an opportunity to work with best-in-class verification, debug tools, Design IP & close collaboration with best protocol experts in the industry. You will work with highly professional and motivated colleagues who value and support your contribution. Requirements: Bachelors/master's with good academic record. 7+ years’ experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a strong work exposure on any of the industry standard protocols like PCIe, USB, Ethernet, MIPI etc.. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 8-15 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: Designing, developing, and troubleshooting core algorithms for word-level synthesis. - Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. - Engaging in pure technical roles focused on software development and architecture. - Implementing multi-threaded and distributed code solutions. - Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. - Enhancing the performance and quality of synthesis tools used globally. - Solving complex logic interference problems to improve design accuracy. - Contributing to the development of high-performance silicon chips and software content. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Familiarity with multi-threaded and distributed code development. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the word-level synthesis team, catering to multiple EDA products. This team focuses on developing innovative solutions to improve synthesis quality of results (QoR), performance, and logic interference. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a Digital Verification Senior Engineer, you are passionate about technology and eager to drive pre-silicon functional verification of High-Speed PHY IPs. You have a dynamic personality and a strong desire to learn and excel in pre-silicon verification activities. With a solid understanding of digital design and HDL implementation, you are ready to take on complex challenges and contribute significantly to our innovative projects. You thrive in a diverse team environment and possess excellent debug and diagnostic skills, along with proficiency in scripting and automation using TCL, PERL, or Python. What You’ll Be Doing: Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You’ll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python. Who You Are: You are a detail-oriented, analytical thinker with a strong problem-solving mindset. You possess excellent communication and collaboration skills, enabling you to work effectively within a diverse team. Your passion for technology drives you to stay updated with the latest advancements and continuously improve your skills. You are proactive, adaptable, and committed to delivering high-quality results in a fast-paced environment. The Team You’ll Be A Part Of: You will join a dedicated team of engineers focused on the verification of High-Speed PHY IPs. Our team is committed to innovation and excellence, working collaboratively to ensure the highest standards of quality and performance. We value diversity and inclusivity, fostering an environment where every team member can thrive and contribute to our collective success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven R&D Engineer with a deep understanding of data structures, algorithms, and their applications. You have a strong background in software development, particularly with C/C++ on UNIX/Linux platforms, and are eager to tackle complex, large-scale software code-based tool development. With a minimum of 8 years of related experience, you have honed your analytical, debugging, and problem-solving skills. You thrive in both self-directed and collaborative environments and are committed to continuous learning and exploration of new technologies. Your excellent communication skills in English enable you to effectively collaborate with team members and present your ideas clearly. What You’ll Be Doing: Supporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality. Applying extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption. Interacting with other Synopsys R&D members and customers to understand their needs and product goals. Contributing to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules. Exercising judgment in developing methods, techniques, and evaluation criteria to meet project goals. Collaborating with a team of enthusiastic and creative engineers to drive innovation and excellence. The Impact You Will Have: Enhancing the performance and quality of our verification tools, leading to increased customer satisfaction and adoption. Driving continuous improvement in software development processes and practices. Contributing to the development of cutting-edge technologies that power innovations in various industries. Helping Synopsys maintain its leadership position in the market by delivering high-performance solutions. Influencing the direction and success of our hardware verification tools through your expertise and innovation. Fostering a collaborative and innovative work environment that encourages growth and learning. What You’ll Need: A Bachelor’s degree in Electrical/Electronics/Computer-Science Engineering with a minimum of 8 years of related experience, or a Master’s degree with 6 years of relevant experience. In-depth understanding of data structures, algorithms, and their applications. Excellent software development experience with C/C++ on UNIX/Linux platforms. Exposure to Python, TCL, and shell scripting languages is preferable. Exposure to HDL languages like Verilog or System Verilog is desirable, with a willingness to learn their nuances. Demonstrated history of good analytical, debugging, and problem-solving skills. Experience with complex and large software code-based tool development. Who You Are: You are a motivated and enthusiastic engineer who excels in both independent and collaborative settings. You have a solid desire to learn and explore new technologies, and you exercise good judgment in developing methods and techniques to meet project goals. Your excellent written and oral communication skills in English enable you to collaborate effectively and present your ideas clearly. Special consideration will be given to candidates with a background in hardware functional verification and/or synthesis techniques, as well as knowledge of software specification, design processes, and regression testing. The Team You’ll Be A Part Of: You will join the Hardware Assisted Verification team at Synopsys, a group of dedicated and innovative engineers focused on developing and enhancing our verification tools. Our team is committed to pushing the boundaries of technology and delivering high-performance solutions that meet the needs of our customers. We work in a collaborative and dynamic environment, where creativity and innovation are encouraged and valued. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 5 -8 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: Designing, developing, and troubleshooting core algorithms for word-level synthesis. - Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. - Engaging in pure technical roles focused on software development and architecture. - Implementing multi-threaded and distributed code solutions. - Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. - Enhancing the performance and quality of synthesis tools used globally. - Solving complex logic interference problems to improve design accuracy. - Contributing to the development of high-performance silicon chips and software content. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Familiarity with multi-threaded and distributed code development. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the word-level synthesis team, catering to multiple EDA products. This team focuses on developing innovative solutions to improve synthesis quality of results (QoR), performance, and logic interference. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Must Have: SV/UVM Test Bentch Developement Any Protocols: (PCI Express or UCIe, CXL or NVM AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM) 8+ years of hands-on DV experience in System Verilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVM AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Job Types: Full-time, Permanent Pay: Up to ₹2,081,539.67 per year Benefits: Health insurance Provident Fund Schedule: Monday to Friday Experience: Design verification : 8 years (Required) Location: Bengaluru, Karnataka (Required) Work Location: In person

Job Title: Memory Circuit Design Verification Engineer / Senior Engineer Location: Hyderabad Experience: 7+ Years Need Immediate -15days joiners Job Summary: We are hiring skilled Memory Circuit Design Verification Engineers to join DRAM & Emerging Memory Group. The ideal candidate will bring expertise in pre-silicon verification of complex gate-level custom memory designs (DRAM, DDR, LPDDR), demonstrate strong debugging skills, and have experience with tools like Verilog, SPICE, System Verilog, and UVM. Key Responsibilities: Perform full-chip/block-level simulation and debugging for memory circuits. Develop testbenches, vectors, and functional test cases to ensure design coverage. Analyze coverage reports and enhance test environments accordingly. Collaborate with global design and verification teams. Contribute to the evolution of verification methodologies. Must-Have Skills: 7+ years in memory circuit verification. Strong fundamentals in CMOS and gate-level design. Hands-on with Verilog and SPICE simulations. Experience with regressions, debugging, and functional coverage analysis. Preferred Skills: System Verilog, UVM test bench development. Knowledge of DRAM/LPDDR4/LPDDR5/DDR4/DDR5 protocols. AMS verification, mixed-signal co-simulation exposure. Scripting skills (Python, Perl). Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related domain. Show more Show less

Job Title: Design Verification Engineer Location: Hyderabad Experience: 3 to 8 Years Job Description: Mirafra Technologies is looking for experienced Design Verification Engineers to join our team in Hyderabad . This role involves a mix of IP-level ownership, feature enhancement, and debug responsibilities. Key Responsibilities: Own design verification at the IP level Plan and execute feature additions and mode re-enablement for specific design variants Perform bug fixes and analyze regression signatures Minimum Qualifications: Proficient in SystemVerilog, UVM, UVM_REG , and advanced debugging techniques Experience reading specifications and developing comprehensive test plans Expertise in building monitors, scoreboards, sequencers, and sequences Skilled in using scripts and verification methodologies to enhance bug detection Strong understanding of functional verification , including test planning, testbench development, stimulus generation, checking, and functional coverage Comfortable with build checks , working with large testbenches , coverage analysis , and adding/enabling debug mechanisms Proactive approach to analyzing failures and identifying root causes Apply Now or send your resume to swarnamanjari@mirafra.com

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 7+ years of DFT experience Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

At TE, you will unleash your potential working with people from diverse backgrounds and industries to create a safer, sustainable and more connected world. Job Overview TE Connectivity s R&D/Product Development Engineering Teams conceive original ideas for new products, introduce them into practice. Overall objective is to perform principle key simulations for new or existing products during the product development process of electromechanical relays. Additionally, support in simulation roadmap development will be carried out. Furthermore, active participation in the simulation centre of competence will further expand the simulation community. Job Responsibilities Supporting product development by means of electromagnetic simulations Supporting product development by means of structural simulations Research and self-study related to simulation roadmap development Cooperation in a dynamic team Participation in a simulation engineering community What your background should look like: B.Tech in Electrical Engineering, Mechanical Engineering or similar. Mtech in similar fields is preferable. Proficient level of English. Sound knowledge of ANSYS products, or similar Sound knowledge of relay basics and electromagnetism. 4+ years of experience in the field of simulations. Proficiency in MS Office. Competencies Location

Implement Web applications in Python/Django Understanding project requirement & converting into technical requirements Independently do the coding/development of complex modules Independent contributor, high quality software within the timelines Ensure high quality releases through appropriate QC and QA activities Participate in technical discussions / reviews Works collaboratively and professionally with other associates in cross functional teams to achieve goals

Key member of design verification team, which has both mixed-signal and digital design verification engineers. The candidate will be responsible for formulating verification strategies and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both INA and ADI. It is expected that he/she will be able to understand and influence other disciplines (analog/digital design) to achieve better all-round chip verification. The candidate is also encouraged to participate in cross company technical initiatives as we'll as patent and publish work where possible Requirements B.Tech/M.Tech with 8+ years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of analog/mixed-signal building blocks such as power management, ADCs, DACs, PLL, bandgap references, oscillators etc and related digital control and signal processing Demonstrated experience of verification plan, verification environment development and verification/debug of complex mixed signal products at chip-top level Experience of co-simulations with analog model/transistor level and digital RTL/Gate+SDFs, experience of circuit simulations with Spice/Fast Spice simulators Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe Responsibilities Come up with verification strategy for a product after going through product requirements and design specifications Interact with digital/analog leads to get agreement on verification strategy Create models for analog/mixed-signal blocks for chip-top verification, tradeoff accuracy Vs speed. Validate models against actual design (self-checking tests) Create verification plans, build verification environment, develop self-checking testcases. Bring up chip top mixed-signal verification environments (AMS and DMS DV environments) Deploy industry standard SV/UVM based metric driven verification approach Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV etc) for first pass silicon Support test and characterization teams in post-silicon validation Collaborate with CAD team to deploy next generation innovative design verification methodologies to reduce overall TTM, mentor junior DV engineers in the team Skill Set [Experience of following is desired, not all but most of them] Modelling of analog blocks - SV-RNM - Verilog-AMS - Schematic based structural models (macro models) - System C Familiarity with analog/mixed-signal design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision Chip-top co-simulation with tools such as Cadence ADE/Cadence AMSD with Spectre as the analog solver and Xcelium as the digital solver Experience and debug with digital simulators such as Cadence Xcelium/Synopsys VCS Experience with Spice/Fast Spice simulators such as Spectre Ultrasim/APS/XPS Experience with SV/UVM (agent creation, env building, score-boarding, RAL etc) Experience with third-party IP integration Tracking of verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager Experience with languages/tools/software relating to product development is an added advantage - C, C++, System C, AMS - Automation with scripting languages: Python/Perl/Shell etc - Embedded programming for on-chip micros or separate MCUs - Matlab/Simulink for system level simulations and modeling