1624 Verilog Jobs - Page 36

Your Role Python Developer As a Python developer you must have 2+ years in Python / Pyspark. Strong programming experience, Python, Pyspark, Scala is preferred. Experience in designing and implementing CI/CD, Build Management, and Development strategy. Experience with SQL and SQL Analytical functions, experience participating in key business, architectural and technical decisions Scope to get trained on AWS cloud technology Your Profile Python SQL Data Engineer What youll love about working here Choosing Capgemini means having the opportunity to make a difference, whether for the worlds leading businesses or for society. It means getting the support you need to shape your career in the way that works for you. It means when the future doesnt look as bright as youd like, you have the opportunity to make changeto rewrite it. When you join Capgemini, you dont just start a new job. You become part of something bigger. A diverse collective of free-thinkers, entrepreneurs and experts, all working together to unleash human energy through technology, for an inclusive and sustainable future. At Capgemini, people are at the heart of everything we do! You can exponentially grow your career by being part of innovative projects and taking advantage of our extensive Learning & Development programs. With us, you will experience an inclusive, safe, healthy, and flexible work environment to bring out the best in you! You also get a chance to make positive social change and build a better world by taking an active role in our Corporate Social Responsibility and Sustainability initiatives. And whilst you make a difference, you will also have a lot of fun. About Capgemini

Requirements Swift, Python, Java, Go, Verilog, Javascript, C++, or C# coding experience required This is a great opportunity to supplement your income while looking for longer or more full-time work, all while contributing to the development of new AI models using your domain expertise! Our client has hired over 1,000 Braintrust talent and intends to hire hundreds more! Many Braintrust coders earn over $12,000 per month! You’ll have the flexibility to work as much or as little as you choose - 20hrs/week is suggested, but not a limit. Start working in as little as 48 hours. Your final hourly rate will be chosen by Outlier AI and determined by your location. What to expect: If qualified, you’ll be invited to complete a brief questionnaire that takes 3-5 minutes. If you successfully pass the questionnaire, you’ll be approved and able to begin work ASAP. Required qualifications: Proficiency working one of the following languages: Swift, Python, Java, Go, Verilog, Javascript, C++, or C# Complete fluency in the English language is required. You should be able to describe code and abstract information in a clear way. Preferred qualifications: Bachelor's and/or Master's degree in Computer Science or equivalent. Students are welcome. Note : Outlier AI is partnering with Remotasks for this opportunity What You’ll Be Working On Our client has partnered with organizations to train AI large language models, helping cutting-edge generative AI models write better code. Example projects might include: Evaluating the quality of AI-generated code, including human-readable summaries of your rationale Solve coding problems, writing functional and efficient code Optimize code to run at maximum efficiency Writing robust test cases to confirm code works efficiently and effectively Writing human-readable summaries of coding problems Writing explanations of how code can solve problems and evaluate various solution approaches No previous experience with AI necessary! You will receive detailed instructions on what is expected of you after you complete the application and verification process. Show more Show less

As CPU/Processor Nest Verification Lead, you will be responsible for the pre-silicon functional and performance verification of our chipsets, covering the CPU core, cache/nest subsystem, memory hierarchy, and other on-silicon IP used in our next-generation IBM Power Systems offerings. You will use state-of-the-art techniques to simulate and verify the designs of these custom microprocessor-based systems. The job uses both hardware and software engineering skills, and entails creating environments and methodologies for simulating the VHDL input, as well as analysis and problem debug. Verification is performed at various levels within the design hierarchy. A background in Electronics / Micro Electronics / Computer Science with strong programming skills is required. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise As a CPU/Processor Nest Verification lead, you will play a pivotal role in the pre-silicon functional and performance verification of our cutting-edge chipsets. Your responsibilities will cover a spectrum of critical areas, including the cache/nest subsystem, interrupt, Fabric, memory hierarchy, and various on-silicon IP integral to our upcoming IBM Power Systems offerings. Leveraging state-of-the-art techniques, you will be at the forefront of simulating and validating the designs of these bespoke microprocessor-based systems and providing technical guidance to junior/mid-level engineers in the team. Key Duties: Verification Environment OwnershipTake charge of the verification environments for microprocessor components, contributing significantly to the identification of functional and performance issues before silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes. Documentation and CommunicationThoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Communicate progress effectively, keeping team members and stakeholders informed of milestones achieved and potential challenges encountered.Lead the development of the verification plans, environment, testbenches and writing testcases for the Cache Coherency Transport Interconnect Fabric in IBM Server Processors. Technical leadership Providing Technical leadership to the senior/mid-level engineers who will be working closely with you. Stakeholder management Managing and influencing stakeholders technically, periodic update in status meeting/technical forums. Functional Verification Experience: 15+ years of extensive experience in functional verification of processors, demonstrating a deep understanding of verification methodologies and technically leading a large team. Computer Architecture Knowledge: Good understanding of computer architecture, including Processor core design specifications, Coherency and Cache Designs, Processor IO subsystem, Interrupt architecture, with expertise in at least any one of the above domains. Multi-processor Cache Coherency Transport Fabric Experience in functional verification of system level Coherency Transport Network designs and ways to stress verify them. Strong programming skills Proficiency in C++, Python scripting or similar languages. Preferred technical and professional experience Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL and general computational logic design and verification concepts. Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design. Experience in specifying and developing the verification infrastructure for verifying processor based designs. Minimum one full life cycle experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect/Fabric Verification. Knowledge of system-level architecture including buses like AXI/ACE/CHI, AMBA interconnects

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 5+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Role & Responsibilities : As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verification plans, environment, testbenches and writing testcases to verify Cache structures & protocols in processor. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. . Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Professional and Technical Expertise : 9 + years of experience in Functional Verification of processors or ASICs. 3+ years of experience in the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor Cache (L2/L3) Coherency, Memory Hierarchy Verification Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Cache Coherency Verification Developed test-plans and test strategies for IP/unit/block level verification of Cache Coherency structures in processor/SoC Good object-oriented programming skills in C++/SV, scripting languages like Python/Perl. Knowledge of functional verification methodology like UVM/OVM Knowledge of HDLs (VHDL/Verilog) Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenarios, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Additional skill Stress testing and ability to identify corner case scenarios.

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Understand the design specification , Memory and Memory BIST engine connections Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Hardware debug skills backed by relevant experience on projects Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , etc Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

The team is responsible for modelling the Power processor and systems which is used to evaluate the performance of new generation Power processor and systems and provide design guidance. The team is also responsible for performance verification and bring up of new Power processor and systems. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise As a Hardware Performance Modelling your responsibilities would be to work on multiple HW performance projects Develop test and validation plan for hardware bringup, pre-silicon performance verification and post-silicon performance validation Develop kernels and methodologies to correlate software model with hardware performance. Interact and collaborate with hardware, software and firmware development teams during system bringup and ensure the system meets its performance objectives Root causing of fails in simulation for performance changes/difference between Hardware and simulator Build automation frameworks, test cases and result analysis scripts. Design and develop model to simulate sub-systems like cache, interconnect and memory protocols Working with Architects/Research teams for optimizing architecture and system design, improving performance of next generation POWER processor and system. Demonstrate leadership in characterizing benchmarks, workloads and use cases (application code), and proposing system design optimisations to improve system level performance. Independently own system unit and successfully drive performance missions. responsibilities would include Excellent coding skills Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! As part of the CAD team our engineers develop and support tools for all of NVIDIAs semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL. Below are some of the some of the teams activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today. What you will be doing: Be responsible for architecting highly automated and customizable design flows using software engineering with modular design and object oriented techniques. Work closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs. Support development of tools using C++/Python/TCL. Work cross functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks. What we need to see: 2+ years of relevant work experience. Smart, diligent and motivated to work in our CAD group. BE or BTech or MTech in Computer Science, or Electronics Engineering, or Electrical Engineering, or equivalent experience. Knowledge or experience with DFT, DFP is a plus. Familiar with Verilog, VLSI and ASIC design principles, including knowledge of logic cells. Software engineering: software design, algorithms, and QA. Strong C++ programming experience. Solid programming and scripting skills in Python or TCL desired. Knowledge of GenAI, LLM, AI Code Generation is a plus. Having strong interpersonal skills will serve you well in this role. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If youre creative and autonomous, we want to hear from you! #LI-Hybrid

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s fueled by great technology and amazing people. Today, we re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. As part of the CAD team our engineers develop and support tools for all of NVIDIAs semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL. Below are some of the some of the teams activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today. What you ll be doing: Develop CAD software for high performance chip design and verification. Develop design and verification methodology for VLSI. Work on next generation software infrastructure for scalable development. Deploy AI into our work flows What we need to see: BS or Master degree of Electrical Engineering/Computer Engineering/Computer Science or equivalent experience 2+ years of relevant work experience. Skill of script language, such as Python/Perl/TCL. Software engineering: software design, algorithms, and QA. Familiar with C++ is a plus. Ways to stand out from the crowd: Familiar with Verilog. Experiences in CAD software developments. Knowledge or experience with DFT, DFP is a plus. Familiar with Verilog, VLSI and ASIC design principles, including knowledge of logic cells. Knowledge of GenAI, LLM, AI Code Generation is a plus. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challengeCome join our GPU Verification team and help us build future interconnect architectures that will continue to drive us forward in the fields of High Performance Computing, Graphics and AI. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. Were united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. #LI-Hybrid What we need to see: B. Tech. / M. Tech or equivalent experience 2+ years of relevant experience Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog Expertise in comprehensive verification of IP or interconnect protocols (e. g. PCI Express, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd: Excellent knowledge of PCIE protocol - Gen3 and above Good understanding of the system level architecture of PCIE/CXL-based designs Perl, Python or similar scripting and SW programming language experience Good debugging and analytical skills Good interpersonal skills dream to work as a great teammate #LI-Hybrid

Lead the unit level pre-silicon functional & performance verification the Load Store Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for LSU, including the Load and Store pipelines, D-Cache, Address translation, out of order execution of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of load store unit verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

- Lead the architecture, design and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 10 to 15 years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design - Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements. - Follow agile project leadership principles. Work with the team on estimation and execution plan. - Ability to quickly understand issues spanning multiple functional domains, switch context frequently and provide solutions to problems, is necessary. Preferred technical and professional experience Bachelors / Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 3,5,7,14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Staff Digital IC Design Engineer - Digital Compute Team About Us At **onsemi** , we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets. The Role We are expanding the team to India and are looking for a **Staff Digital IC Design Engineer with experiences in the development of embedded MCU/DSP systems** . You will develop and benchmark such systems for a variety of processor cores and consult the product integration teams during the integration of these solutions into semiconductor products. Why Join Us We create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. We offer competitive benefit package and a great place to work. You will be able to build up a career in a successful international company, and you can participate in interesting international projects. What You ll Do + Architect, specify, implement, simulate, and benchmark MCU and DSP systems as well as hardware accelerators + Consult the product integration teams in the definition, the integration and use of these systems + Participate to the verification and FPGA prototyping of these systems + Coordinate the SDK development with the software team + Lead project activities + Contribute to design methodology and design flow improvements What You ll Need + Minimum BS/MS in Electrical Engineering or related technical field + At least 8 years of relevant work experience in semiconductor product development including engineering leadership + Experience with embedded CPUs (e.g. ARM Cortex, DSP), AMBA bus protocols (AHB/APB). + RTL design of digital IP blocks and systems in Verilog/SystemVerilog + Technical document writing + Excellent English written and verbal communication skills. \#LI-RT1 **onsemi** (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. **More details about our company benefits can be found here:** https: / / www.onsemi.com / careers / career-benefits We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

Job Description As an FPGA Engineer specialised in RTL (Register Transfer Level) coding, you will be responsible for designing, optimising, and implementing hardware solutions on Field-Programmable Gate Arrays (FPGAs) to support high-frequency trading strategies. You will work closely with the trading systems team to develop and deploy ultra-low latency trading infrastructure, ensuring the highest levels of performance, reliability, and efficiency. Key Responsibilities RTL Design and Optimisation: Design and optimise FPGA-based solutions using RTL coding techniques to achieve ultra-low latency and high throughput for trading algorithms and strategies. Algorithm Implementation: Implement trading algorithms and strategies in hardware, leveraging FPGA capabilities to minimise latency and maximise performance. Hardware Acceleration: Identify opportunities for hardware acceleration of critical trading functions and develop FPGA-based solutions to achieve significant speedups. Performance Analysis and Tuning: Conduct performance analysis of FPGA designs, identify bottlenecks, and fine-tune the implementations to achieve optimal performance. Hardware Integration: Collaborate with software engineers and system architects to integrate FPGA-based solutions into the overall trading infrastructure, ensuring seamless operation and compatibility. Testing and Validation: Develop test benches and perform thorough testing and validation of FPGA designs to ensure correctness, reliability, and robustness under real-world trading conditions. Documentation and Reporting: Document FPGA designs, methodologies, and implementation details, and provide regular reports and updates to stakeholders on project progress and performance metrics. Requirements Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL. Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable. Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus. Strong analytical and problem-solving skills, with the ability to optimise designs for performance, power, and resource utilisation. Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment. Show more Show less

Job Details Job Description: Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/with: Silicon Design and/or Validation/Verification. Preferred Qualifications Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. Show more Show less

Job Details Job Description: Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications :- are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or school. work/classes/research. Education Requirement:- Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9 years of industry work experience, or- Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5 years of related work experience. Minimum Qualifications:- 8+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth know how. Solid work experience in designing, verifying, and validating complex hardware systems. Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python. Proficient in debugging SOC, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designs. Knowledge of advanced computer architecture and micro-architecture concepts. Experience with writing directed and random test cases. Experience with design verification and validation methodologies and strategies. Good communication skills, and a team player. Able to work independently in a fast-paced team and environment. Desired Requirements- Deep knowledge of system architecture including CPU, Data path packet processing flows , Boot Flows, fabrics, interconnects, NOC, memory sub-systems, I/O peripherals (UART/SPI), bus protocols (AXI/APB), PCIE, Ethernet, DMA, CSRs, etc. MACsec , Time-Sensitive Networking (TSN) Experience with boot, reset, clock, and power management. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. Show more Show less

Job Details Job Description: This position is for an experienced, motivated, and passionate circuit design engineer with expertise in the area of custom circuits memories, SSARF SRAM, Register File, ROM design for GHI CCG SAI Circuits Team. In this position you will be working in a team responsible for delivering high quality designs for graphics projects. You would also be involved in key decisions finalizing the memory architecture that best meets the design requirements of the program, technical readiness involving circuit simulations and responsibility for implementation as well as convergence of the design while meeting high circuit quality. The key responsibilities include ownership of tools, flows, methodologies as well as coming up with innovative design implementations with focus on power and area reduction. The role would require deep understanding of transistor and circuit behavior, strong communication, problem solving skills, time management and multitasking skills. The team members have also an opportunity to diversify their skills into other custom circuits as well as working with the client in integration of the custom circuits. Qualifications Minimum Qualifications: Minimum 4-7 years of experience in designing and delivering of SRAM's/RF's/ROM's. Understanding of semiconductor device physics; VLSI Technology and VLSI circuits (analog/digital), Familiarity with spice simulations and Verilog and other tools for design and development of memory IP's like ESPCV, Nanotime, Nova, Totem etc. Knowledge of scripting (PERL/TCL/Python) is desirable, Preferred Educational Qualifications: ME/Mtech/MS in Microelectronics/VLSI Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. Show more Show less

Description for Internal Candidates Staff Digital IC Design Engineer - Digital Compute Team About Us At onsemi , we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets. The Role We are expanding the team to India and are looking for a Staff Digital IC Design Engineer with experiences in the development of embedded MCU/DSP systems . You will develop and benchmark such systems for a variety of processor cores and consult the product integration teams during the integration of these solutions into semiconductor products. Why Join Us We create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. We offer competitive benefit package and a great place to work. You will be able to build up a career in a successful international company, and you can participate in interesting international projects. What You’ll Do Architect, specify, implement, simulate, and benchmark MCU and DSP systems as well as hardware accelerators Consult the product integration teams in the definition, the integration and use of these systems Participate to the verification and FPGA prototyping of these systems Coordinate the SDK development with the software team Lead project activities Contribute to design methodology and design flow improvements What You’ll Need Minimum BS/MS in Electrical Engineering or related technical field At least 8 years of relevant work experience in semiconductor product development including engineering leadership Experience with embedded CPUs (e.g. ARM Cortex, DSP), AMBA bus protocols (AHB/APB). RTL design of digital IP blocks and systems in Verilog/SystemVerilog Technical document writing Excellent English written and verbal communication skills. #LI-RT1 onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. More details about our company benefits can be found here: https://www.onsemi.com/careers/career-benefits We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work. Responsibilities for Internal Candidates What Else You May Bring Experience in some of the following areas is a plus: Project/task leadership Design of CPU/MCU (sub)systems, SystemRDL or IP-XACT Programming in Python for automation and in C/C++ for embedded software Design intent (timing constraints/SDC, power intent/UPF) Design of signal processing components RTL to GDS flow, including logic synthesis, place-and-route, STA, power analysis Advanced digital verification methodology (e.g. UVM) Our commitment to you As part of the onsemi team, you will have an opportunity to transform your tomorrow and operate in a diverse, inclusive, and socially responsible environment. If you’re passionate about shaping a better future, join us and define your future! #LI-RT1