5 Vclp Jobs

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of whats next in electronics and the world. Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude,?openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier . At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make peoples lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark Join Renesas. Lets Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

You should have a strong understanding of design power intent at the RTL level and UPF. You should be able to translate power intent into UPF after consulting with the RTL designers. Your responsibilities will include running, debugging, and resolving Static Power Check (VCLP) related issues independently before RTL is handed off to PD. Your tasks will involve UPF generation (yaml creation, running upfgen to create the UPF) and UPF maintenance. As RTL changes, UPF may need adjustments and re-verification. You should also be proficient in running VCLP and integrating it with the top level as well as with the P&R flows. We are looking for a UPF expert with a strong background in low power design. We require UPF expertise as a primary skill, not as a secondary one. It is acceptable to have one back end and one front end with PNR, guided by one consultant. The responsibilities include RTL UPF coding, LP validation, level shifter strategy, and potentially handling UPF within the PNR flows. If the candidate is not familiar with PNR flows, we can fill that gap with a back end UPF person.,

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. Your responsibilities will include developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs will be a key part of your role. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler, you will solve critical design challenges and collaborate with a global team to stay ahead of technological advancements. Your impact will be significant as you advance the state-of-the-art in high-performance core and IP implementation, enhance the performance and efficiency of Synopsys" design methodologies and tools, and enable the development of cutting-edge semiconductor technologies at advanced nodes. You will contribute to the successful delivery of high-quality, high-performance IPs to the market, drive innovation, and support Synopsys" mission to lead in chip design, verification, and IP integration. To excel in this role, you will need deep knowledge of synthesis, timing closure, power optimization, and constraints management, along with experience in low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX, as well as familiarity with scripting languages such as TCL, Perl, and Python, are essential. A BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience will further strengthen your qualifications. You are a detail-oriented and innovative engineer with a passion for pushing the limits of technology. Your problem-solving skills, ability to optimize design processes, and effective collaboration with a global team set you apart. Motivated by continuous improvement and making a significant impact in the field of semiconductor design, you are well-suited to join the growing global team at Synopsys dedicated to advancing high-performance core and IP implementation.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 2 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques. Experience with a scripting language such as Perl or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience. Experience implementing image/video processing blocks or other multimedia IPs such as Display or ISP Experience with Application-Specific Integrated Circuit (ASIC) design methodologies for clock domain checks and reset checks Experience in scripting languages, C/C++ programming and software design skills. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes Micro architecture, RTL coding, definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for quality and optimized security designs. You will be involved in Micro-Arch and RTL coding for imaging and video codecs - IPs and subsystems. You will also contribute to improvements by debugging and by using different RTL QC tools like Lint, CDC, VCLP. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks. Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis. Develop RTL implementations that meet competitive power, performance and area targets. Participate in synthesis, timing/power closure and Field-Programmable Gate Array (FPGA) or silicon bring-up. Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture or micro-architecture planning. ,

Greetings from Quest Global Please find the details and kindly send me your Profile . RTL Design 10-15 Years Location : Bangalore/Hyderabad 1. Should have worked on ASIC/SOC projects using 22nm or smaller technology node 2. Expertise in automated RTL Integration using any of the industry standard tool/EDA flow 3. Expertise in SDC and UPF constraints development and checking 4. Expertise in Timing violation debug/fix at netlist level 5. Good knowledge on AHB/AXI/APB/PIPE interface 6. Expertise in Lint, CDC and VCLP, Synthesis, LEC 7. Very Strong in Python and TCL scripting • Nice to have skills: 8. Exposure to PCIe/Ucie 9. Experience in Leading small rtl design team • Location: Bangalore and Hyderabad • Notice period: max 45 days Please forward your updated profile to chakradhar.marupuru@quest-global.com below details Current CTC : Expected CTC: Notice Period : Best Regards Chakradhar M , Email:chakradhar.marupuru@quest-global.com | www.quest-global.com. Assistant Manager Quest Global Whatsapp No : 99869 21214 , Mob: +601 736 16576 Quest Global, Penang – Mayang. Unit 1.13-17 GBS@Mayang , Lengkok Mayang Pasir, Bayan Baru 11950,Penang, Malaysia