128 Upf Jobs

You will be working as a Core MS Specialist at Scorpedge Global IT Services in Chennai, TN. Your primary responsibility will involve managing day-to-day tasks associated with Microsoft technologies and systems. This includes providing technical support, troubleshooting issues, and performing maintenance activities to ensure the smooth functioning and reliability of IT systems. To excel in this role, you should have experience as a Cloud Deployment Engineer with expertise in CBIS deployment. Additionally, you should possess a good understanding of Openstack/AWS, along with strong troubleshooting and fault handling skills. Experience as a Charging Engineer with hands-on experience in Fault/Configuration handling in PCRF/RA/NCC/NPC will be beneficial for this role. Moreover, familiarity with Paco 5G SA and expertise in Nokia products, specifically in AMF/SMF/UPF/CMM/CMG, will be advantageous. It is important to note that hybrid experience is not required for this position, as the focus is on WFO in the NAM region. Ideally, this position is based in Chennai and involves working in 24*7 shifts following the NAM Shift schedule.,

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team that has experienced significant growth. We are seeking talented engineers to join us in Bangalore/Hyderabad, India and be a part of our exciting journey in the SysMoore era. **Design Lead:** In the role of an RTL Design lead, you will experience the thrill of achieving bug-free RTL from requirements or specifications. Your expertise in driving the design effort for complex IP/Subsystem/SoC blocks, with a track record of multiple tape-outs, will be invaluable in delivering high-quality results. **Verification Lead:** As a Verification lead, you will enjoy the challenge of identifying and rectifying bugs to ensure the design intent is realized. Your role is critical in ensuring the flawless operation of chips, such as those on space telescopes capturing stunning images of galaxies. Your experience in leading multiple tape-outs and closing verifications of complex IP/Subsystem/SoC blocks will be instrumental in our success. **Design role:** In the position of a Senior RTL Subsystems Designer Lead with over 8 years of experience, you will be responsible for driving the Subsystem life cycle from requirements to final release phases. This includes crafting functional specifications, defining micro-architectures, coding RTL using best practices, conducting RTL quality checks, collaborating with Verification and implementation teams, and overseeing project completion. Proficiency in standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as hands-on experience in low power design and understanding of DFT requirements and architecture are essential. Your ability to work effectively with cross-functional teams will be crucial in delivering successful projects. **Verification role:** In the role of a Senior Verification lead with over 8 years of experience, you will lead the complete Verification cycle by crafting test plans, architecting verification environments, developing test infrastructure, and executing plans to closure with coverage. Proficiency in Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as power-aware Verification with UPF, is required. Hands-on experience in Gate Level Verification is a valuable addition. Your collaboration with cross-functional teams will be key to driving projects to completion.,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

The role of (VLSI) Design Verification (DV) involves working on functional specifications of IPs, subsystems, and SOC. You will be responsible for reviewing and revising designs, utilizing System Verilog and UVM for verification. Your tasks will include performing RTL simulations using Synopsys and Cadence simulators, as well as working with UPF. We are looking for candidates who can join immediately and hold a degree in BE, B.Tech, ME, or M.Tech. This position is based in Bangalore, Hyderabad, Kochin, and Pune. If you are interested in this opportunity, please reach out to us at career@krazymantra.com.,

As an Electrical Engineer or Computer Science professional with a Bachelor's degree and 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon, you will have the opportunity to contribute to the innovation behind Google's direct-to-consumer products. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Your responsibilities will include defining the microarchitecture of IPs, Subsystems, or SOCs, working with cross-functional teams to ensure quality, schedule compliance, and PPA optimized design. You will collaborate with Verification, Design for Test, Physical Design, and Software teams to make design decisions and represent project status throughout the development process. Additionally, you will define block-level design documents such as interface protocols, block diagrams, transaction flows, and pipelines. You will be responsible for RTL coding for SS/SOC integration, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Working with key design collaterals such as SDC and UPF, you will negotiate the right collateral quality and identify solutions in collaboration with stakeholders. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or equivalent practical experience, experience with chip design flow and cross-domain involving DV, DFT, Physical Design, and software. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip-level verification will be advantageous. Knowledge in areas such as Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin-muxing is also beneficial. Join a team that pushes boundaries and works towards developing custom silicon solutions that power the future of Google's products, loved by millions worldwide. Contribute your skills and expertise to create radically helpful experiences by combining the best of Google AI, Software, and Hardware. Be a part of a team that aims to make people's lives better through technology.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to develop implementation strategies that meet quality, schedule, and power performance area requirements for sub-system/chip-level integration. - Collaborating with the subsystem team to plan SOC milestones, quality checks, and guide subsystem teams with SOC level requirements such as IPXACT, CSR, Lint, CDC, SDC, UPF, etc. - Engaging with a cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and provide project status updates throughout the development process. To be successful in this role, you should have a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. You should also have at least 3 years of experience in RTL coding using Verilog or SystemVerilog language, with experience in high-performance design, multi-power domains with clocking. Preferred qualifications include experience with multiple SoCs with silicon success, knowledge of ASIC design methodologies for front quality checks, and domain expertise in areas such as Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux. Additionally, an understanding of cross-domain activities involving domain validation, design for testing, physical design, and software will be beneficial. Join us at Google and be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Help us research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to make people's lives better through technology.,

You should have a strong understanding of design power intent at the RTL level and UPF. You should be able to translate power intent into UPF after consulting with the RTL designers. Your responsibilities will include running, debugging, and resolving Static Power Check (VCLP) related issues independently before RTL is handed off to PD. Your tasks will involve UPF generation (yaml creation, running upfgen to create the UPF) and UPF maintenance. As RTL changes, UPF may need adjustments and re-verification. You should also be proficient in running VCLP and integrating it with the top level as well as with the P&R flows. We are looking for a UPF expert with a strong background in low power design. We require UPF expertise as a primary skill, not as a secondary one. It is acceptable to have one back end and one front end with PNR, guided by one consultant. The responsibilities include RTL UPF coding, LP validation, level shifter strategy, and potentially handling UPF within the PNR flows. If the candidate is not familiar with PNR flows, we can fill that gap with a back end UPF person.,

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

Candidate should have relevant technical experience on Packet Core Domain (4G EPC and 5G Core Nodes - AMF, SMF, UPF, NRF, NSSG, AUSF and LTE Nodes - MME, EPG - SGW/PGW, PCRF). Excellent knowledge on LTE and 5G EPC / 5G Core Architecture - Interface and Protocols. Must have Hands on Experience on testing E2E call flows - and demonstrate troubleshooting and analysis skills. Excellent understanding of Testing concepts, Defect Management, Test Metrics and reporting to stakeholders. Excellent Communication skills good stakeholder management skills Good to have Skills Knowledge on Linux and commands. Basic knowledge of Kubernetes. Using any traffic simulator (AAT, Dallas, Spirent etc. Test Management and Defect Management Tool like JIRA. Automation experience in Packet Core Domain.

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. Your role will involve RTL Design and implementation of interface logic between PCIe controller and DMA engines for high-performance networking applications. You will be creating block-level micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance throughout the design flow. In addition to your technical responsibilities, you will also need to work and communicate effectively with multi-site teams. Your experience in ASIC product life cycle, including requirements, design, implementation, test, and post-silicon validation, will be essential in this role. If you are passionate about technology solutions and enjoy working in a collaborative environment, we encourage you to apply for this position. Join us at MarvyLogic and be a part of building futuristic and impactful solutions that make a difference in various industries. Your experience with emerging technologies and your contributions to our team may help you evolve both professionally and personally, leading to a more fulfilling life.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience 3+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools * Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking * Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus * Should be sincere, dedicated and willing to take up new challenges Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus 6+ years experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Project Role : Tech Delivery Subject Matter Expert Project Role Description : Drive innovative practices into delivery, bring depth of expertise to a delivery engagement. Sought out as experts, enhance Accentures marketplace reputation. Bring emerging ideas to life by shaping Accenture and client strategy. Use deep technical expertise, business acumen and fluid communication skills, work directly with a client in a trusted advisor relationship to gather requirements to analyze, design and/or implement technology best practice business changes. Must have skills : 5G Wireless Networks & Technologies Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time educationJob Title:5G Core Network Ops Specialist Summary :We are seeking a skilled 5G Core Network Specialist to join our team. The ideal candidate will have extensive experience with Nokia 5G Core platforms and will be responsible for fault handling, troubleshooting, session and service investigation, configuration review, performance monitoring, security support, change management, and escalation coordination.Roles and Responsibilities:1.Fault Handling & Troubleshooting:Provide Level 2 (L2) support for 5G Core SA network functions in production environment.Analyze alarms from NetAct/Mantaray, or external monitoring tools.Correlate events using Netscout, Mantaray, and PM/CM data.Troubleshoot and resolve complex issues related to registration, session management, mobility, policy, charging, DNS, IPSec and Handover issues.Handle node-level failures (AMF/SMF/UPF/NRF/UDM/UDR/SDL/PCF/CHF/Flowone, Nokia EDR restarts, crashes, overload).Handle troubleshooting on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).Perform packet tracing (Wireshark) or core trace (PCAP, logs) and Nokia PCMD trace capturing and analysis.Perform root cause analysis (RCA) and implement corrective actions.Handle escalations from Tier-1 support and provide timely resolution.2.Session & Service Investigation:Trace subscriber issues (5G attach, PDU session, QoS).Use tools like EDR, Flow Tracer, Nokia Cloud Operations Manager (COM).Correlate user-plane drops, abnormal release, bearer QoS mismatch.Work on Preventive measures with L1 team for health check & backup. 3.Configuration and Change Management:Create a MOP for required changes, validate MOP with Ops teams, stakeholders before rollout/implementation.Maintain detailed documentation of network configurations, incident reports, and operational procedures.Support software upgrades, patch management, and configuration changes.Maintain documentation for known issues, troubleshooting guides, and standard operating procedures (SOPs).Audit NRF/PCF/UDM etc configuration & Database.Validate policy rules, slicing parameters, and DNN/APN settings.Support integration of new 5G Core nodes and features into the live network.4.Performance Monitoring:Use KPI dashboards (NetAct/NetScout) to monitor 5G Core KPIs e.g registration success rate, PDU session setup success, latency, throughput, user-plane utilization.Proactively detect degrading KPIs trends.5.Security & Access Support:Application support for Nokia EDR and CrowdStrike.Assist with certificate renewal, firewall/NAT issues, and access failures.6.Escalation & Coordination:Escalate unresolved issues to L3 teams, TAC, OSS/Core engineering.Work with L3 and care team for issue resolution.Ensure compliance with SLAs and contribute to continuous service improvement. 7.ReportingGenerate daily/weekly/monthly reports on network performance, incident trends, and SLA compliance. Technical Experience and Professional Attributes:812 years of experience in Telecom industry with hands on experience in 5G Core.Mandatory experience with Nokia 5G Core-SA platform.Solid understanding for 5G Core Packet Core Network Protocol such as N1, N2, N3, N6, N7, N8, 5G Core interfaces, GTP-C/U, HTTPS and including ability to trace, debug the issues.Hands-on experience with 5GC components:AMF, SMF, UPF, NRF, AUSF, NSSF, UDM, PCF, CHF, UDR, SDL, Nokia EDR, Provisioning and Flowone.Troubleshooting and configuration hands on experience on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).In-depth understanding of 3GPP call flows for 5G-SA, 5G NSA, Call routing, number analysis, system configuration, call flow, Data roaming, configuration and knowledge of Telecom standards e.g. 3GPP, ITU-T and ANSI.Familiarity with policy control mechanisms, QoS enforcement, and charging models (event-based, session-based).Hands-on experience with Diameter, HTTP/2, REST APIs, and SBI interfaces.Strong analytical and troubleshooting skills.Proficiency in monitoring and tracing tools (NetAct, NetScout, PCMD tracing). And log management systems (e.g., Prometheus, Grafana).Knowledge of network protocols and security (TLS, IPsec).Excellent communication and documentation skills. Educational Qualification:BE / BTech15 Years Full Time Education Additional Information:Nokia certifications (e.g., NCOM, NCS, NSP, Kubernetes).Experience in Nokia Platform 5G Core, NCOM, NCS, Nokia Private cloud and Public Cloud (AWS preferred), cloud-native environments (Kubernetes, Docker, CI/CD pipelines).Cloud Certifications (AWS)/ Experience on AWS Cloud Qualification 15 years full time education

Project Role : Tech Delivery Subject Matter Expert Project Role Description : Drive innovative practices into delivery, bring depth of expertise to a delivery engagement. Sought out as experts, enhance Accentures marketplace reputation. Bring emerging ideas to life by shaping Accenture and client strategy. Use deep technical expertise, business acumen and fluid communication skills, work directly with a client in a trusted advisor relationship to gather requirements to analyze, design and/or implement technology best practice business changes. Must have skills : 5G Wireless Networks & Technologies Good to have skills : Software Defined Network and OperationsMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time educationJob Title:5G Core Network Ops Specialist Summary :We are seeking a skilled 5G Core Network Specialist to join our team. The ideal candidate will have extensive experience with Nokia 5G Core platforms and will be responsible for fault handling, troubleshooting, session and service investigation, configuration review, performance monitoring, security support, change management, and escalation coordination.Roles and Responsibilities:1.Fault Handling & Troubleshooting:Provide Level 2 (L2) support for 5G Core SA network functions in production environment.Analyze alarms from NetAct/Mantaray, or external monitoring tools.Correlate events using Netscout, Mantaray, and PM/CM data.Troubleshoot and resolve complex issues related to registration, session management, mobility, policy, charging, DNS, IPSec and Handover issues.Handle node-level failures (AMF/SMF/UPF/NRF/UDM/UDR/SDL/PCF/CHF/Flowone, Nokia EDR restarts, crashes, overload).Handle troubleshooting on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).Perform packet tracing (Wireshark) or core trace (PCAP, logs) and Nokia PCMD trace capturing and analysis.Perform root cause analysis (RCA) and implement corrective actions.Handle escalations from Tier-1 support and provide timely resolution.2.Session & Service Investigation:Trace subscriber issues (5G attach, PDU session, QoS).Use tools like EDR, Flow Tracer, Nokia Cloud Operations Manager (COM).Correlate user-plane drops, abnormal release, bearer QoS mismatch.Work on Preventive measures with L1 team for health check & backup. 3.Configuration and Change Management:Create a MOP for required changes, validate MOP with Ops teams, stakeholders before rollout/implementation.Maintain detailed documentation of network configurations, incident reports, and operational procedures.Support software upgrades, patch management, and configuration changes.Maintain documentation for known issues, troubleshooting guides, and standard operating procedures (SOPs).Audit NRF/PCF/UDM etc configuration & Database.Validate policy rules, slicing parameters, and DNN/APN settings.Support integration of new 5G Core nodes and features into the live network.4.Performance Monitoring:Use KPI dashboards (NetAct/NetScout) to monitor 5G Core KPIs e.g registration success rate, PDU session setup success, latency, throughput, user-plane utilization.Proactively detect degrading KPIs trends.5.Security & Access Support:Application support for Nokia EDR and CrowdStrike.Assist with certificate renewal, firewall/NAT issues, and access failures.6.Escalation & Coordination:Escalate unresolved issues to L3 teams, TAC, OSS/Core engineering.Work with L3 and care team for issue resolution.Ensure compliance with SLAs and contribute to continuous service improvement. 7.ReportingGenerate daily/weekly/monthly reports on network performance, incident trends, and SLA compliance. Technical Experience and Professional Attributes:812 years of experience in Telecom industry with hands on experience in 5G Core.Mandatory experience with Nokia 5G Core-SA platform.Solid understanding for 5G Core Packet Core Network Protocol such as N1, N2, N3, N6, N7, N8, 5G Core interfaces, GTP-C/U, HTTPS and including ability to trace, debug the issues.Hands-on experience with 5GC components:AMF, SMF, UPF, NRF, AUSF, NSSF, UDM, PCF, CHF, UDR, SDL, Nokia EDR, Provisioning and Flowone.Troubleshooting and configuration hands on experience on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).In-depth understanding of 3GPP call flows for 5G-SA, 5G NSA, Call routing, number analysis, system configuration, call flow, Data roaming, configuration and knowledge of Telecom standards e.g. 3GPP, ITU-T and ANSI.Familiarity with policy control mechanisms, QoS enforcement, and charging models (event-based, session-based).Hands-on experience with Diameter, HTTP/2, REST APIs, and SBI interfaces.Strong analytical and troubleshooting skills.Proficiency in monitoring and tracing tools (NetAct, NetScout, PCMD tracing). And log management systems (e.g., Prometheus, Grafana).Knowledge of network protocols and security (TLS, IPsec).Excellent communication and documentation skills. Educational Qualifications:BE / BTech15 Years Full Time Education Additional Information:Nokia certifications (e.g., NCOM, NCS, NSP, Kubernetes).Experience in Nokia Platform 5G Core, NCOM, NCS, Nokia Private cloud and Public Cloud (AWS preferred), cloud-native environments (Kubernetes, Docker, CI/CD pipelines).Cloud Certifications (AWS)/ Experience on AWS Cloud Qualification 15 years full time education

Project Role : Tech Delivery Subject Matter Expert Project Role Description : Drive innovative practices into delivery, bring depth of expertise to a delivery engagement. Sought out as experts, enhance Accentures marketplace reputation. Bring emerging ideas to life by shaping Accenture and client strategy. Use deep technical expertise, business acumen and fluid communication skills, work directly with a client in a trusted advisor relationship to gather requirements to analyze, design and/or implement technology best practice business changes. Must have skills : 5G Wireless Networks & Technologies Good to have skills : Software Defined Network and OperationsMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time educationJob Title:5G Core Network Ops SME Summary :We are seeking a skilled 5G Core Network SME to join our team. The ideal candidate will have extensive experience with Nokia 5G Core platforms and will be responsible for fault handling, troubleshooting, session and service investigation, configuration review, performance monitoring, security support, change management, and escalation coordination.Roles and Responsibilities:1.Fault Handling & Troubleshooting:Provide Level 2 (L2) support for 5G Core SA network functions in production environment.Analyze alarms from NetAct/Mantaray, or external monitoring tools.Correlate events using Netscout, Mantaray, and PM/CM data.Troubleshoot and resolve complex issues related to registration, session management, mobility, policy, charging, DNS, IPSec and Handover issues.Handle node-level failures (AMF/SMF/UPF/NRF/UDM/UDR/SDL/PCF/CHF/Flowone, Nokia EDR restarts, crashes, overload).Handle troubleshooting on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).Perform packet tracing (Wireshark) or core trace (PCAP, logs) and Nokia PCMD trace capturing and analysis.Perform root cause analysis (RCA) and implement corrective actions.Handle escalations from Tier-1 support and provide timely resolution.2.Session & Service Investigation:Trace subscriber issues (5G attach, PDU session, QoS).Use tools like EDR, Flow Tracer, Nokia Cloud Operations Manager (COM).Correlate user-plane drops, abnormal release, bearer QoS mismatch.Work on Preventive measures with L1 team for health check & backup. 3.Configuration and Change Management:Create a MOP for required changes, validate MOP with Ops teams, stakeholders before rollout/implementation.Maintain detailed documentation of network configurations, incident reports, and operational procedures.Support software upgrades, patch management, and configuration changes.Maintain documentation for known issues, troubleshooting guides, and standard operating procedures (SOPs).Audit NRF/PCF/UDM etc configuration & Database.Validate policy rules, slicing parameters, and DNN/APN settings.Support integration of new 5G Core nodes and features into the live network.4.Performance Monitoring:Use KPI dashboards (NetAct/NetScout) to monitor 5G Core KPIs e.g registration success rate, PDU session setup success, latency, throughput, user-plane utilization.Proactively detect degrading KPIs trends.5.Security & Access Support:Application support for Nokia EDR and CrowdStrike.Assist with certificate renewal, firewall/NAT issues, and access failures.6.Escalation & Coordination:Escalate unresolved issues to L3 teams, TAC, OSS/Core engineering.Work with L3 and care team for issue resolution.Ensure compliance with SLAs and contribute to continuous service improvement. 7.ReportingGenerate daily/weekly/monthly reports on network performance, incident trends, and SLA compliance. Technical Experience and Professional Attributes:1218 years of experience in Telecom industry with hands on experience in 5G Core.Mandatory experience with Nokia 5G Core-SA platform.Solid understanding for 5G Core Packet Core Network Protocol such as N1, N2, N3, N6, N7, N8, 5G Core interfaces, GTP-C/U, HTTPS and including ability to trace, debug the issues.Hands-on experience with 5GC components:AMF, SMF, UPF, NRF, AUSF, NSSF, UDM, PCF, CHF, UDR, SDL, Nokia EDR, Provisioning and Flowone.Troubleshooting and configuration hands on experience on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).In-depth understanding of 3GPP call flows for 5G-SA, 5G NSA, Call routing, number analysis, system configuration, call flow, Data roaming, configuration and knowledge of Telecom standards e.g. 3GPP, ITU-T and ANSI.Familiarity with policy control mechanisms, QoS enforcement, and charging models (event-based, session-based).Hands-on experience with Diameter, HTTP/2, REST APIs, and SBI interfaces.Strong analytical and troubleshooting skills.Proficiency in monitoring and tracing tools (NetAct, NetScout, PCMD tracing). And log management systems (e.g., Prometheus, Grafana).Knowledge of network protocols and security (TLS, IPsec).Excellent communication and documentation skills. Educational Qualifications:BE / BTech15 Years Full Time Education Additional Information:Nokia certifications (e.g., NCOM, NCS, NSP, Kubernetes).Experience in Nokia Platform 5G Core, NCOM, NCS, Nokia Private cloud and Public Cloud (AWS preferred), cloud-native environments (Kubernetes, Docker, CI/CD pipelines).Cloud Certifications (AWS)/ Experience on AWS Cloud Qualification 15 years full time education

Project Role : Tech Delivery Subject Matter Expert Project Role Description : Drive innovative practices into delivery, bring depth of expertise to a delivery engagement. Sought out as experts, enhance Accentures marketplace reputation. Bring emerging ideas to life by shaping Accenture and client strategy. Use deep technical expertise, business acumen and fluid communication skills, work directly with a client in a trusted advisor relationship to gather requirements to analyze, design and/or implement technology best practice business changes. Must have skills : 5G Wireless Networks & Technologies Good to have skills : Software Defined Network and OperationsMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time educationJob Title:5G Core Network Ops SME Summary :We are seeking a skilled 5G Core Network SME to join our team. The ideal candidate will have extensive experience with Nokia 5G Core platforms and will be responsible for fault handling, troubleshooting, session and service investigation, configuration review, performance monitoring, security support, change management, and escalation coordination.Roles and Responsibilities:1.Fault Handling & Troubleshooting:Provide Level 2 (L2) support for 5G Core SA network functions in production environment.Analyze alarms from NetAct/Mantaray, or external monitoring tools.Correlate events using Netscout, Mantaray, and PM/CM data.Troubleshoot and resolve complex issues related to registration, session management, mobility, policy, charging, DNS, IPSec and Handover issues.Handle node-level failures (AMF/SMF/UPF/NRF/UDM/UDR/SDL/PCF/CHF/Flowone, Nokia EDR restarts, crashes, overload).Handle troubleshooting on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).Perform packet tracing (Wireshark) or core trace (PCAP, logs) and Nokia PCMD trace capturing and analysis.Perform root cause analysis (RCA) and implement corrective actions.Handle escalations from Tier-1 support and provide timely resolution.2.Session & Service Investigation:Trace subscriber issues (5G attach, PDU session, QoS).Use tools like EDR, Flow Tracer, Nokia Cloud Operations Manager (COM).Correlate user-plane drops, abnormal release, bearer QoS mismatch.Work on Preventive measures with L1 team for health check & backup. 3.Configuration and Change Management:Create a MOP for required changes, validate MOP with Ops teams, stakeholders before rollout/implementation.Maintain detailed documentation of network configurations, incident reports, and operational procedures.Support software upgrades, patch management, and configuration changes.Maintain documentation for known issues, troubleshooting guides, and standard operating procedures (SOPs).Audit NRF/PCF/UDM etc configuration & Database.Validate policy rules, slicing parameters, and DNN/APN settings.Support integration of new 5G Core nodes and features into the live network.4.Performance Monitoring:Use KPI dashboards (NetAct/NetScout) to monitor 5G Core KPIs e.g registration success rate, PDU session setup success, latency, throughput, user-plane utilization.Proactively detect degrading KPIs trends.5.Security & Access Support:Application support for Nokia EDR and CrowdStrike.Assist with certificate renewal, firewall/NAT issues, and access failures.6.Escalation & Coordination:Escalate unresolved issues to L3 teams, TAC, OSS/Core engineering.Work with L3 and care team for issue resolution.Ensure compliance with SLAs and contribute to continuous service improvement. 7.ReportingGenerate daily/weekly/monthly reports on network performance, incident trends, and SLA compliance.Technical Skills and Professional Attributes:1218 years of experience in Telecom industry with hands on experience in 5G Core.Mandatory experience with Nokia 5G Core-SA platform.Solid understanding for 5G Core Packet Core Network Protocol such as N1, N2, N3, N6, N7, N8, 5G Core interfaces, GTP-C/U, HTTPS and including ability to trace, debug the issues.Hands-on experience with 5GC components:AMF, SMF, UPF, NRF, AUSF, NSSF, UDM, PCF, CHF, UDR, SDL, Nokia EDR, Provisioning and Flowone.Troubleshooting and configuration hands on experience on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).In-depth understanding of 3GPP call flows for 5G-SA, 5G NSA, Call routing, number analysis, system configuration, call flow, Data roaming, configuration and knowledge of Telecom standards e.g. 3GPP, ITU-T and ANSI.Familiarity with policy control mechanisms, QoS enforcement, and charging models (event-based, session-based).Hands-on experience with Diameter, HTTP/2, REST APIs, and SBI interfaces.Strong analytical and troubleshooting skills.Proficiency in monitoring and tracing tools (NetAct, NetScout, PCMD tracing). And log management systems (e.g., Prometheus, Grafana).Knowledge of network protocols and security (TLS, IPsec).Excellent communication and documentation skills. Educational Qualification:BE / BTech15 Years Full Time Education Additional Information:Nokia certifications (e.g., NCOM, NCS, NSP, Kubernetes).Experience in Nokia Platform 5G Core, NCOM, NCS, Nokia Private cloud and Public Cloud (AWS preferred), cloud-native environments (Kubernetes, Docker, CI/CD pipelines).Cloud Certifications (AWS)/ Experience on AWS Cloud Qualification 15 years full time education

Project Role : Tech Delivery Subject Matter Expert Project Role Description : Drive innovative practices into delivery, bring depth of expertise to a delivery engagement. Sought out as experts, enhance Accentures marketplace reputation. Bring emerging ideas to life by shaping Accenture and client strategy. Use deep technical expertise, business acumen and fluid communication skills, work directly with a client in a trusted advisor relationship to gather requirements to analyze, design and/or implement technology best practice business changes. Must have skills : 5G Wireless Networks & Technologies Good to have skills : Software Defined Network and OperationsMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time educationJob Title:5G Core Network Ops Specialist Summary :We are seeking a skilled 5G Core Network Specialist to join our team. The ideal candidate will have extensive experience with Nokia 5G Core platforms and will be responsible for fault handling, troubleshooting, session and service investigation, configuration review, performance monitoring, security support, change management, and escalation coordination.Roles and Responsibilities:1.Fault Handling & Troubleshooting:Provide Level 2 (L2) support for 5G Core SA network functions in production environment.Analyze alarms from NetAct/Mantaray, or external monitoring tools.Correlate events using Netscout, Mantaray, and PM/CM data.Troubleshoot and resolve complex issues related to registration, session management, mobility, policy, charging, DNS, IPSec and Handover issues.Handle node-level failures (AMF/SMF/UPF/NRF/UDM/UDR/SDL/PCF/CHF/Flowone, Nokia EDR restarts, crashes, overload).Handle troubleshooting on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).Perform packet tracing (Wireshark) or core trace (PCAP, logs) and Nokia PCMD trace capturing and analysis.Perform root cause analysis (RCA) and implement corrective actions.Handle escalations from Tier-1 support and provide timely resolution.2.Session & Service Investigation:Trace subscriber issues (5G attach, PDU session, QoS).Use tools like EDR, Flow Tracer, Nokia Cloud Operations Manager (COM).Correlate user-plane drops, abnormal release, bearer QoS mismatch.Work on Preventive measures with L1 team for health check & backup. 3.Configuration and Change Management:Create a MOP for required changes, validate MOP with Ops teams, stakeholders before rollout/implementation.Maintain detailed documentation of network configurations, incident reports, and operational procedures.Support software upgrades, patch management, and configuration changes.Maintain documentation for known issues, troubleshooting guides, and standard operating procedures (SOPs).Audit NRF/PCF/UDM etc configuration & Database.Validate policy rules, slicing parameters, and DNN/APN settings.Support integration of new 5G Core nodes and features into the live network.4.Performance Monitoring:Use KPI dashboards (NetAct/NetScout) to monitor 5G Core KPIs e.g registration success rate, PDU session setup success, latency, throughput, user-plane utilization.Proactively detect degrading KPIs trends.5.Security & Access Support:Application support for Nokia EDR and CrowdStrike.Assist with certificate renewal, firewall/NAT issues, and access failures.6.Escalation & Coordination:Escalate unresolved issues to L3 teams, TAC, OSS/Core engineering.Work with L3 and care team for issue resolution.Ensure compliance with SLAs and contribute to continuous service improvement. 7.ReportingGenerate daily/weekly/monthly reports on network performance, incident trends, and SLA compliance. Technical Experience and Professional Attributes:812 years of experience in Telecom industry with hands on experience in 5G Core.Mandatory experience with Nokia 5G Core-SA platform.Solid understanding for 5G Core Packet Core Network Protocol such as N1, N2, N3, N6, N7, N8, 5G Core interfaces, GTP-C/U, HTTPS and including ability to trace, debug the issues.Hands-on experience with 5GC components:AMF, SMF, UPF, NRF, AUSF, NSSF, UDM, PCF, CHF, UDR, SDL, Nokia EDR, Provisioning and Flowone.Troubleshooting and configuration hands on experience on 5G Core Database, UDM, UDR, SDL, Provisioning, Flowone, CHF(Charging), PCF(Policy).In-depth understanding of 3GPP call flows for 5G-SA, 5G NSA, Call routing, number analysis, system configuration, call flow, Data roaming, configuration and knowledge of Telecom standards e.g. 3GPP, ITU-T and ANSI.Familiarity with policy control mechanisms, QoS enforcement, and charging models (event-based, session-based).Hands-on experience with Diameter, HTTP/2, REST APIs, and SBI interfaces.Strong analytical and troubleshooting skills.Proficiency in monitoring and tracing tools (NetAct, NetScout, PCMD tracing). And log management systems (e.g., Prometheus, Grafana).Knowledge of network protocols and security (TLS, IPsec).Excellent communication and documentation skills. Educational Qualification:BE / BTech15 Years Full Time Education Additional Information:Nokia certifications (e.g., NCOM, NCS, NSP, Kubernetes).Experience in Nokia Platform 5G Core, NCOM, NCS, Nokia Private cloud and Public Cloud (AWS preferred), cloud-native environments (Kubernetes, Docker, CI/CD pipelines).Cloud Certifications (AWS)/ Experience on AWS Cloud Qualification 15 years full time education

The culture at MarvyLogic is defined by its people. We foster a culture of passion for technology solutions that have a direct impact on businesses. We prioritize the pursuit of individual passions among our employees. Working with us offers you the opportunity to gain a comprehensive understanding of various industries and cutting-edge technologies. This exposure enables us to develop solutions that are not only forward-thinking but also highly impactful. Being a part of MarvyLogic can facilitate your personal growth, leading you towards a more fulfilling life. You should possess a Graduate Degree in Electrical/Electronics Engineering with over 10 years of experience (a post Graduate degree would be an added advantage). The job location is in Bengaluru/Bangalore. As a candidate for this position, you are expected to have a minimum of 10 years of experience in ASIC RTL Design and demonstrate proficiency in Verilog/System Verilog. Your expertise should extend to working with multiple clock and power domains. You should have a strong background in integrating and validating high-speed PCIe IP cores, including controllers and PHY SerDes. Experience with PCIe protocol analyzers and debugging is essential, as well as familiarity with PCIe driver and application software for both Linux and Windows environments. Your responsibilities will include RTL design and implementation of interface logic between PCIe controllers and DMA engines for high-performance networking applications. You will be required to create block-level micro-architecture specifications detailing interfaces, timing behavior, design tradeoffs, and performance objectives. Additionally, you will need to review vendor IP integration guidelines and ensure compliance throughout the design process. Running integrity check tools such as Lint/CDC/DFT/LEC/UPF to meet coding and implementation standards will also be part of your role. You will play a crucial role in the design verification process by reviewing test plans, coverage reports, writing assertions, and implementing design modifications to enhance verification quality. Furthermore, you will be involved in the physical implementation process by providing synthesis constraints, timing exceptions, and making design updates to achieve area, power, and performance targets. Key Responsibilities: - Collaborate effectively with multi-site teams - Conduct reviews of FPGA netlist releases (block/chip) - Demonstrate experience in the full ASIC product life cycle, including requirements, design, implementation, testing, and post-silicon validation.,

The job is located in Bangalore and requires 3-5 years of experience for 2 available positions. The primary responsibility involves RTL Design, with a focus on practical experience in RTL development using VHDL and/or Verilog. This includes functional and structural RTL design, design partitioning, simulation, regression, and collaboration with design verification teams. The ideal candidate should be familiar with the latest RTL languages and tools such as Modelsim, VCS, Design Compile, Prime Time, Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, among others. Desirable experience includes strong processor architecture knowledge, microarchitecture implementation, microprocessor integration, and low power design. Effective communication skills, teamwork abilities, self-direction, and time management skills are essential for this role. Preferred qualifications include developing RTL for multiple logic blocks of a DSP core, running various frontend tools for linting, clock domain crossing, and synthesis, collaborating with the physical design team on design constraints and timing closure, working with the power team on power optimization, and collaborating with the verification team on test plan, coverage plan, and coverage closure. The educational requirement for this position is a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field.,

As a highly motivated and innovative digital design engineer at Synopsys, you will play a crucial role in driving the innovations that shape the future in the Era of Pervasive Intelligence. Your expertise in ASIC design methodology and flows, particularly focusing on low power analysis and optimization, will be instrumental in empowering the creation of high-performance silicon chips and software content. With a proven track record in working with advanced nodes, especially at 5nm and below, you will be responsible for developing and driving digital design methodologies to achieve the lowest power consumption. Your strong background in both digital and physical design, coupled with your proficiency in developing timing constraints and UPF, will enable you to meet stringent power, timing, and area targets effectively. Collaborating closely with design teams and EDA tools teams, you will contribute to enhancing the power efficiency of high-performance silicon chips and driving innovation in low power design methodologies. Your role will involve conducting SAIF-based analysis, implementing best practices for low power design, and optimizing RTL designs to achieve optimal power consumption. To excel in this role, you will need to possess an MSEE or BSEE with over 20 years of digital design experience, including 15+ years of digital and/or physical design experience. Your expertise in low-power design techniques at RTL, proficiency in EDA tool flows, and excellent software and scripting skills (Perl, Tcl, Python) will be key to your success in this position. As part of the Digital Methodology Center of Excellence within Synopsys" IP team, you will collaborate with experienced engineers to develop cutting-edge digital design methodologies used across all IP development teams. Your organizational and communication skills, coupled with your ability to think and communicate at different levels of abstraction, will be essential in contributing to the successful implementation of advanced node technologies and industry-leading mixed-signal products. In addition to the challenging and rewarding work environment, Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

Qualcomm India Private Limited is a company of inventors that unlocked 5G, leading to rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. In the Invention Age, inventive minds with diverse skills, backgrounds, and cultures are needed to turn 5G's potential into world-changing technologies and products. As part of the successful engineering team at Qualcomm, whose deliveries are present in billions of mobile, compute, and IoT products globally, you will play a crucial role. This position, based in Qualcomm's Bangalore office, focuses on Low Power controller IP cores and subsystem digital design for industry-leading Snapdragon SoCs in mobile, compute, IoT, and Automotive markets. Your responsibilities will include micro-architecture and RTL design for Cores/subsystems, working closely with various teams for design convergence, enabling SW teams to utilize HW blocks, qualifying designs using static tool checks, and reporting progress against expectations. Preferred qualifications for this role include 4 to 10 years of experience in digital front-end design, expertise in RTL coding in Verilog/SV/VHDL, familiarity with UPF and power domain crossing, experience in synthesis, logical equivalence checks, and netlist CLP, proficiency in various bus protocols, low power design methodology, formal verification, and post-Si debug. Additionally, expertise in scripting languages like Perl/TCL/Python, database management flows, and effective communication skills are desired. Minimum qualifications entail a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of relevant experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. The company expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualified applicants are encouraged to apply, and staffing/recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.