SMTS/Principal ASIC Design Engineer

The culture at MarvyLogic is defined by its people. We foster a culture of passion for technology solutions that have a direct impact on businesses. We prioritize the pursuit of individual passions among our employees. Working with us offers you the opportunity to gain a comprehensive understanding of various industries and cutting-edge technologies. This exposure enables us to develop solutions that are not only forward-thinking but also highly impactful. Being a part of MarvyLogic can facilitate your personal growth, leading you towards a more fulfilling life. You should possess a Graduate Degree in Electrical/Electronics Engineering with over 10 years of experience (a post Graduate degree would be an added advantage). The job location is in Bengaluru/Bangalore. As a candidate for this position, you are expected to have a minimum of 10 years of experience in ASIC RTL Design and demonstrate proficiency in Verilog/System Verilog. Your expertise should extend to working with multiple clock and power domains. You should have a strong background in integrating and validating high-speed PCIe IP cores, including controllers and PHY SerDes. Experience with PCIe protocol analyzers and debugging is essential, as well as familiarity with PCIe driver and application software for both Linux and Windows environments. Your responsibilities will include RTL design and implementation of interface logic between PCIe controllers and DMA engines for high-performance networking applications. You will be required to create block-level micro-architecture specifications detailing interfaces, timing behavior, design tradeoffs, and performance objectives. Additionally, you will need to review vendor IP integration guidelines and ensure compliance throughout the design process. Running integrity check tools such as Lint/CDC/DFT/LEC/UPF to meet coding and implementation standards will also be part of your role. You will play a crucial role in the design verification process by reviewing test plans, coverage reports, writing assertions, and implementing design modifications to enhance verification quality. Furthermore, you will be involved in the physical implementation process by providing synthesis constraints, timing exceptions, and making design updates to achieve area, power, and performance targets. Key Responsibilities: - Collaborate effectively with multi-site teams - Conduct reviews of FPGA netlist releases (block/chip) - Demonstrate experience in the full ASIC product life cycle, including requirements, design, implementation, testing, and post-silicon validation.,