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Qualcomm
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Sr Lead High-Speed Interface PHY IP Digital Design Engineer

Sr Lead High-Speed Interface PHY IP Digital Design Engineer

Qualcomm

3 - 8 years

5 - 10 Lacs

Bengaluru

Posted:3 weeks ago| Platform:

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Skills Required

rtl design cdc hardware engineering lint dft dsp physical design circuit usb soc atpg digital design rtl development vhdl fpga protocols system verilog synthesis sta altera netlist rtl uvm verilog functional verification serdes rf fpga design pcie

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Responsibilities

Front-End implementation of SERDES high speed Interface PHY designs

RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.

Work with functional verification team on test-plan development and debug.

Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA.

UPF writing, power aware equivalence checks and low power checks.

DFT insertion and ATPG analysis for optimal SAF, TDF coverage.

Provide support to SoC integration and chip level pre/post-silicon debug.

Skills & Experience

MTech/BTech in EE/CS with hardware engineering experience of 4 to 7 years.

Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA.

Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable.

Experience with post-silicon bring-up and debug is a plus.

Able to work with teams across the globe and possess good communication skills.

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Sr Lead High-Speed Interface PHY IP Digital Design Engineer