34 Silicon Validation Jobs

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 3 years of experience with functional tests for silicon validation (e.g., C, C++ or Python) or developing embedded software.. Experience in silicon bring up, functional validation, characterizing, and qualifying silicon.. Experience with board schematics, layout, and debug methodologies using lab equipment.. Preferred qualifications:. Experience in hardware/software integration (i.e. pre-silicon use of emulation and software-based test and diagnostics development).. Experience in scripting languages, such as Python for Automation development.. Experience with Power Characterization, PCIe, DDR.. Experience in RTL design, verification or emulation.. Knowledge of SoC architecture, including boot flows.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will be responsible for post-silicon validation of the Cloud TPU projects. You will create test plans and test content for exercising the various subsystems in the AI/ML SoC, verify the content on pre-silicon platforms, execute the tests on post-silicon platforms, and triage and debug issues. You will work closely with engineers from architecture, design, design verification, and software/firmware teams. You will be validating the functional, power, performance, and electrical characteristics of the Cloud Tensor Processing Unit (TPU) silicon to help deliver quality designs for next generation data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.. Responsibilities. Develop and execute tests in post-silicon validation and on HW emulators and assist in bring-up processes from prototyping through post-silicon validation.. Drive debugging and investigation efforts to root-cause cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bring up and production.. Ensure validation provides necessary functional coverage for confident design.. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

MTS/SMTS SILICON DESIGN ENGINEER THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. THE PERSON: The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE: Proficient in IP or Sub-system level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. Experience in RAL is preferred ACADEMIC CREDENTIALS: Bachelor s or master s degree in Electronics or Electrical or Computer engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance .

Memory Architecture: In-depth knowledge of memory design architectures, including SRAM, DRAM, Flash, and other non-volatile memory types. Circuit Design: Expertise in designing memory cells, sense amplifiers, decoders, and other associated memory circuit blocks. Process Technology: Familiarity with advanced CMOS technology nodes and their impact on memory design, including scaling challenges. Design Optimization: Experience in optimizing memory for performance, power, and area, including techniques for reducing leakage and improving access times. Verification & Validation: Proficient in memory verification techniques, including corner analysis, reliability testing, and post-silicon validation. EDA Tools: Hands-on experience with memory design tools, including Cadence, Synopsys, and Mentor Graphics. Yield Enhancement: Knowledge of yield enhancement techniques, including redundancy and error correction codes (ECC). Expectations from the Role: Technical Leadership: Strong technical leadership skills with the ability to guide and mentor junior team members. Problem-Solving: Excellent problem-solving abilities, particularly in diagnosing and resolving memory design challenges. Innovation: Ability to innovate and drive improvements in memory design, balancing performance and manufacturability. Collaboration: Strong communication and teamwork skills, with the ability to work effectively with cross-functional teams. Project Focus: Ability to manage and prioritize multiple projects, ensuring timely

Job Title: Analog Design Engineer / Lead Location: Location: Bengaluru/Bhubaneswar/Ranchi Experience: 5 - 10 Years Technical Requirements: Analog Circuit Design: Strong expertise in designing and simulating analog circuits such as amplifiers, ADCs/DACs, voltage regulators, PLLs, and other mixed-signal Tools & Methodologies: Proficient in using EDA tools for schematic capture, circuit simulation (e.g., SPICE), layout, and post-layout verification. Layout Techniques: Deep understanding of analog layout techniques, including matching, noise reduction, and parasitic minimization. Design for Performance: Experience in optimizing designs for low power, high speed, and area efficiency. Process Knowledge: Familiarity with CMOS process technology, including the impact of process variations on analog performance. Verification & Validation: Skilled in analog/mixed-signal verification methodologies, including behavioral modeling and corner case analysis. Tape-Out Experience: Experience with silicon validation and characterization, including working through tape-out processes. Expectations from the Role: Problem-Solving: Strong analytical and problem-solving skills, with the ability to troubleshoot complex circuit issues. Collaboration: Effective communication and teamwork skills, with the ability to collaborate with digital and layout teams. Attention to Detail: High attention to detail to ensure design accuracy and Innovation: Ability to innovate and optimize designs within the constraints of the Project Management: Ability to manage multiple tasks and projects, ensuring timely

Validating and Debug the ULTRA Low Power Designs Bare Metal or Linux Driver Development Firmware Development C Programming Handle Lab Equipments Testing on Software and Hardware Integration on Both Pre and Post Silicon

Develop Software and Firmware for the following: 1.Server memory subsystem initialization and operation 2.Enabling memory characterization activities 3.Validating memory initialization procedure 4.Automating characterization and post silicon validation work flow Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Masters in Software Systems/ECE/Computer Science Engineering/ with atleast 5 years related experience Bachelors in Software Systems/ECE/Computer Science Engineering/ with atleast 7 years related experience Strong programming expertise in Python, C/ C++, with a proven ability to develop efficient, reliable, and high-performance software solutions. Experience in memory sub-system & post-silicon validation is a definite advantage. Knowledge of modern OS kernel (Linux, AIX) Source control - GIT/Gerrit Good to haveDatabase, MySQL, LAMP

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Job Responsibilities Translate the design specification to an optimal micro-architecture for digital blocks RTL coding using Verilog and System Verilog Meet power, performance and area goals by micro-architecture optimization Block level Designer verification Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Work closely with DFT and PD teams for signoff Support Silicon validation Position requirements BE/BS/Mtech/M.E/PhD degree in Electrical/Electronics/Computer science from a reputed institute 3-10 years of relevant experience Digital logic design and hands-on RTL coding experience, simulation, debug Experience in writing and debugging timing constraints at block and full-chip level Experience in Synthesis and LEC Good verbal and written communication skills to work effectively with teams spread geographically Experience in digital signal processing and Matlab modeling is highly desirable Experience in Processor subsystem design /SOC is a plus

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . Required Skills: Strong software development and architecture skills (Python, C# or similar) Hands-on experience with test and measurement equipment, measurement techniques and test automation Firmware development skills (C and/or assembly language) Strong analog and digital circuit analysis skills Excellent troubleshooting and debug skills Self-driven with a strong work ethic and sense of accountability Experience Level: 4- 6 Years i n Industry Preferred Skills: Knowledge of ARM/8051 architectures and typical MCU peripherals Experience with schematics capture and layout tools (Allegro/Altium/PADS) Post-silicon validation experience Exposure to security standards and security testing Personal profile : Enthusiastic and curious, likes to figure out how things work and prove it Methodical, thorough and dedicated to quality Good verbal and written communication skills Comfortable with cooperating across functional groups Entrepreneurial and problem solver Team player Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Post Silicon & System Validation Engineer The Battery Management System team within the automotive BU is looking for a highly skilled Silicon and System Validation Engineers based in Bengaluru, India who will be responsible for executing the silicon and system validation activities for our next generation of high-performance product portfolio. Context on the role: As a Silicon Validation Engineer, you will perform a full range of product development activities including, but not limited to: Job Duties: Understand the product requirements, develop and execute the BMS IC validation plan Apply the domain knowledge of BMS systems and customer insights into product validation plan development and execution. Design and build custom test hardware to evaluate the battery management silicon and system products. Debug and resolve system issues with cross functional team from design, test, and applications. Collaborate in a dynamic team environment to learn and deploy best practices in application development Requirements*: BS/BEE or MTech in Electrical Engineering, Electronics Engineering with 5 to 8 years of Industrial work Experience in the post silicon validation. Experience developing test plan, test cases, building test environment and executing test plans against silicon and system level specifications.

Job Details: : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications: Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or schoolwork/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6-8 years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5-7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of related work experience. Minimum Qualifications- 4+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth experience. 4+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools. 4+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE. 4+ years of experience in OVM/UVM for developing verification test benches and constrained random verification. Preferred Qualifications- Experience with PCIe, Power Management, Ethernet, Network packet processing. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications: Bachelor Degree in Electrical and Electronics Engineering or Masters Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or school work/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 10+ years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9+ years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 8+ years of related work experience.Minimum Qualifications- 9+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth know how. Solid work experience in designing, verifying, and validating complex hardware systems. Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python. Proficient in debugging SOC, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designs. Knowledge of advanced computer architecture and micro-architecture concepts. Experience with writing directed and random test cases. Experience with design verification and validation methodologies and strategies. Good communication skills, and a team player. Able to work independently in a fast-paced team and environment. Desired - Deep knowledge of system architecture including CPU, Data path packet processing flows , Boot Flows, fabrics, interconnects, NOC, memory sub-systems, I/O peripherals (UART/SPI), bus protocols (AXI/APB), PCIE, Ethernet, DMA etc. Experience with boot, reset, clock and power management. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

You will be part of SoC - Silicon Validation team, particularly running High Volume Validation on given project Working experience with test management web servers and regression reports automation. Contact at Shubhanshi@incise.in Required Candidate profile Basics of ARM SoC architecture, Multicore/Multiprocessor with SMP/heterogenous cores Hands on Python, C programming, test automation programming Using JTAG based debuggers, compilers/linker

There is energy here energy you can feel crackling at any of our international locations. It s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on RD, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.Responsibilities Skills There is energy here energy you can feel crackling at any of our international locations. It s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on RD, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Lattice Semiconductor is seeking a Design Engineer-2 FPGA Architecture to join the Architecture team focused on FPGA architecture modeling and advance system architecture. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role specifics: This is a full-time individual contributor position located in Pune, India. The role will focus on FPGA projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in architecture modeling and evaluation of Lattice FPGA s and Software tools to measure performance, power, and area for various workloads The qualified candidate will be expert in driving Subsystem development and ensure design meets high standards of quality and reliability, conduct regular reviews and audits The role requires working closely with Software tools team to define benchmarks, measure performance and suggest improvement areas Serve as a technical expert, providing guidance and support to other engineers. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and open-minded student Accountabilities: Serve as a key contributor to build FPGA architecture modeling and evaluation platform efforts Drive logic design of key FPGA workloads and bring best-in-class methodologies to accelerate design and test time and quality. Develop the regression testing framework to execute, measure and report architecture modeling and evaluation experiments Ensuring design quality throughout project development conducting regular reviews and audits Perform architecture evaluation of competitive products Work with cross functional team including program management, Software Tools, HW architects, pre and post silicon validation to drive the program Develop strong relationships with worldwide teams. Drive continuous improvement initiatives, staying up to date with the latest industry trends and technologies Occasional travel as needed. Required Skills: BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 3+ years of experience in driving logic design across a multitude of FPGA projects. Expertise in FPGA designs, use-cases, and design considerations, defining micro-architecture and experience of working with various EDA tools Experience in leading the project throughout design cycle and working with cross organization Proven ability to work with multiple groups across different sites and time zones. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones.

Tessolve Semiconductor Pvt Ltd is looking for Sr Post Silicon Validation Engineer _ REQ_ to join our dynamic team and embark on a rewarding career journey Leads validation efforts for advanced silicon across multiple subsystems Creates automation frameworks and comprehensive test suites Drives debug efforts and collaborates closely with design verification teams Ensures compliance with product requirements and launch timelines

Tessolve Semiconductor Pvt Ltd is looking for Post Silicon Validation Engineer _ REQ_ to join our dynamic team and embark on a rewarding career journey Executes validation of silicon chips post-fabrication to ensure performance Develops test plans, scripts, and diagnostic procedures for hardware Collaborates with design and firmware teams for bug triage and resolution Uses lab tools and validation platforms to ensure silicon quality

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Job Description: Analog Devices Automotive group is seeking a highly motivated individual with a strong blend of embedded systems knowledge, hardware/software development skills, EMI/EMC expertise, excellent communication abilities, and a willingness to work in a dynamic environment. This role involves collaborating with teams to facilitate product adoption at Automotive OEMs. Roles & Responsibilities: Create reference designs and customize software/hardware solutions to meet customer-specific requirements for ADI Connectivity Products. Conduct system-level validation by developing necessary hardware/software and performing EMI/EMC pre-compliance tests. Validate functional and system-level performance, ensuring compliance for proprietary serial interfaces. Engage with T1/OEMs (onsite/offsite) to address technical challenges in automotive connectivity products and expedite their transition to production. Develop technical articles, demo platforms, and provide training to customers and ADI sales/support teams. Serve as a vital link between the customer base and ADI product development teams, providing inputs for next-generation products. Understand system-level needs for targeted market/application spaces and collaborate with stakeholders on new product definition and execution. Develop drivers and application code for ADI Connectivity Products. Qualifications & Requirements: Masters/bachelor s degree in electrical/electronic engineering with 2-4 years of experience in the semiconductor industry, preferably in the automotive systems domain. Mandatory experience in C programming. Hands-on experience in bench and system-level validation for silicon validation preferably for a Microcontroller or DSP. Strong knowledge in electronics engineering and familiarity with industry-standard protocols like I2C, I2S, SPI, UART. Hands-on experience in automotive EMI/EMC testing or knowledge of EMI/EMC tests is an added advantage. Experience in automotive ethernet, signal processing algorithm implementation and optimization on processors and connectivity interfaces is a plus. Strong teamwork, interpersonal, and communication skills are essential. Good organizational skills and the ability to multi-task projects/customer activities and set priorities. Highly motivated, innovative, and positive attitude. Willingness to travel domestically or internationally (10% - 15%).

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a "CPU Core Validation Engineer" you would be part of CPU Validation team in CPU org working on validation of CPU core pipeline arch and micro arch features. Roles and Responsibilities Develop detailed test plan considering the IP arch and uarch features. Work with CPU design and verification teams to develop CPU bring up and functional validation test plans for the IP owned. Develop validation methodology and test contents to exercise on emulators during pre-Si phase and on Silicon.Work with SOC bring up teams, software teams to plan CPU core features bringup and end to end validation. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringups. Minimum BA/BS degree in CS/EE with 5+ years experience. 3+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools.Preferred Good understanding of micro-processor architecture, in domains such asCache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management.Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness.Experience in writing Test plans and Assembly code.Ability to develop and work independently on a block/unit of the design. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include, Interface with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 2-6 years experience in ASIC/DFT-simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG -coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim. Expertise in scripting languages such as Perl, shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools, methodologies.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Silicon Validation Lead - Graphics Silicon Team, Bangalore The Qualcomm Graphics Silicon Team in Bangalore is seeking a Silicon Validation Lead. Our power-efficient GPU solutions are fundamental to enabling exciting new markets such as Virtual Reality (VR), Internet of Things (IoT), Artificial Intelligence (AI), drones, and autonomous driving. We are looking for a talented Silicon Lead to deliver power-optimized, high-quality, high-performance graphics and computing solutions. The Graphics Silicon team in Bangalore is part of a global team responsible for developing and delivering GPU solutions that set industry benchmarks. Qualcomm boasts a strong portfolio of GPU cores, providing engineers with the opportunity to work with a world-class engineering team that leads the industry through innovation and disciplined execution. Roles and Responsibilities As a GPU Silicon Validation Engineer, you will be part of the GPU Silicon Team and drive: The new feature, use case enablement, and their validation. Collaboration with GPU design and verification teams to develop GPU bring-up and validation test plans. Preparation for GPU bring-up through pre-work on emulation and FPGA platforms. Coordination with SoC bring-up teams and software teams to plan GPU bring-up. Triage and debugging of failures on silicon. Development of test contents and testing strategies to assist in the validation of GPU on silicon. Working with GPU verification teams to reproduce silicon failures on emulators and FPGAs. Collaboration with the design team to suggest and architect new debug features to improve future GPU bring-ups. Power and performance characterization of GPU. Planning and implementation of new efficiency improvement methodologies in GPU. Qualifications The ideal candidate should possess deep knowledge of scripting and software languages, including PERL/TCL, Linux/Unix shell, and C. Minimum Qualifications Bachelor's or Masters degree in Electrical or Electronic Engineering from a reputed institution. Over 14 years of experience in silicon validation and bring-up. Minimum Strong understanding of microprocessor architecture. Strong understanding of power management. Experience in silicon bring-up and validation of GPU features. Experience in debugging functional, power, performance, and/or physical design issues in silicon. Experience in GPU silicon validation and debug basics. Experience in test development for validation of GPU features on silicon. Experience in developing test vectors for tester bring-up. Implementation of assembly, C, and Python language programming. Experience with HW tools like JTAG, Kratos, LA, Emulation platforms, DMM, etc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a " CPU Core Validation Engineer " you would be part of CPU Validation team in CPU org working on v alidation of CPU core pipeline arch and micro arch features. Roles and Responsibilities Develop detailed test plan considering the IP arch and uarch features. Work with CPU design and verification teams to develop CPU bring up and functional validation test plans for the IP owned. Develop validation methodology and test contents to exercise on emulators during pre-Si phase and on Silicon. Work with SOC bring up teams, software teams to plan CPU core features bringup and end to end validation. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringups. Minimum BA/BS degree in CS/EE with 5+ years experience. 3+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. "‹ Preferred Good understanding of micro-processor architecture, in domains such asCache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness. Experience in writing Test plans and Assembly code. Ability to develop and work independently on a block/unit of the design. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a "CPU Silicon Bring up and Validation Engineer" you would be part of the CPU Silicon Bringup Team, within the CPU team. The charter for CPU Silicon Bringup team would be to prepare for and support bring up of every SoC using the Custom CPUs - from first Silicon through to productization. Roles and Responsibilities Work with CPU design and verification teams to develop CPU bring up and validation test plans. Prepare for CPU bring up through pre-work on emulation and FPGA platforms. Work with SOC bring up teams, software teams to plan CPU bring up. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringups. Minimum : BA/BS degree in CS/EE with 5+ years experience. 3+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. Preferred : Strong understanding of micro-processor architecture. Strong understanding of power management, physical design concepts. Experience in Silicon bring up and validation of CPU features. Experience in debug of functional, power, performance and/or physical design issues in silicon. Experience in CPU design and verification. Experience in Test development for validation of CPU features on Silicon. Experience in development of test vectors for tester bring up. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include , Interfac e with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF) , transition fault (TDF ) models through the use of on-chip test compression techniques. M BIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBI ST verification using unit delay and min/max timing corner s imulations . Work with the P roduct /Test engineering teams on the delivery of manufacturi ng test patterns for ATE . Responsible for supporting post silicon debug effort, issue resolution . Responsible for Diagnostic Tool generation for ATPG , MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 1-6 year s experience in ASIC/DFT - simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG - coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim . Expertise in scripting languages such as Perl , shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools , methodologies. Ability to do multi-tasking & work on several high priority designs in parallel

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. : Our team is at the forefront of Silicon level HW architectural validation, tasked with uncovering design implementation bugs through rigorous pre/post-silicon system level validation. We are seeking a dynamic individual with 5 to 8 years of experience in defining and validating/executing Display specific SoC level use cases and scenarios. The ideal candidate will be instrumental in SOC validation, focusing on Display validation to ensure seamless functionality and performance. Responsibilities: Understand HDDs, PRDs, micro architecture document, create Validation/Test plan, develop content, and execute to validate Display IP and integration at the system level on emulation and the post-silicon environment. Collaborate closely with cross-functional teams to develop, validate targeted tests/UCs on pre and post-silicon platform and for any debugs that requires. Execute Validation plan, Protocol and Electrical Compliance for Display ports. Get in-depth knowledge of IP and its feature integration into SoC to validate and debug using lab tools like display (DP/HDMI/DSI) analyzers, oscilloscope, and silicon debug tools. Job Qualifications: Bachelor's/Master's in Electrical/Electronic Engineering or Computer Engineering. 8-12 years of relevant industry experience in Multimedia preferably Display and its associated interfaces, defining and executing SOC level use cases and scenarios. Proficiency in C/C++ & Python programming for content development and scripting. Familiarity with ARM SoC concepts and architecture specifications like SMMU, GIC, Coresight. Strong debugging skills, with experience using Lab Equipment such as Protocol Analyzer, Logic Analyzers, Oscilloscopes, and Lauterbach debuggers. Experience with multimedia IP basics such as DPU, DSI, DP, GPU, ISP and with emulation platforms, FPGAs, or silicon bring up. Familiarity with display concepts, interfaces and power or performance measurement of SoCs. Excellent communication, interpersonal, and problem-solving skills, with the ability to quickly adapt to new environments and technologies

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities : Design and lead high speed IP (USB3, PCIE, DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development - analog design, layout, digital design, documentation and silicon validation. Would be required to participate in customer facing discussions. Requirements B. Tech/BE/ME/Mtech Exp - 4 +yrs Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc. Must have participated in full cycles of analog IP creation - right from spec to silicon debug and char Must have good communication skills and should be team player. Working experience in PHY (PCIE, USB2, USB3) development is desired We re doing work that matters. Help us solve what others can t.