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Allegis Group
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RTL Software testing

RTL Software testing

Allegis Group

2 - 6 years

8 - 15 Lacs

Hyderabad

Posted:13 hours ago| Platform:

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Skills Required

Testing And Debugging RTL FPGA Vivado Verilog testing Perl RTL Coding TCL Xilinx System Verilog Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role : RTL Software Testing Engineer

Role does not involve Silicon RTL development and neither any HW flow or testing.

Work Location: Hyderabad

Qualification:

Experience Level : Minimum 2+ years

Excellent Knowledge in Tcl, Python scripting. to test cases.(This would be the primary responsibility)
Vivado testing of synthesis tool and other stages.
RTL Coding in Verilog, System Verilog, or VHDL
Strong understanding of FPGA flow, Logic design, Digital design etc.
Knowledge in Xilinx FPGA architecture

Communication Skills:

Ability to communicate technical information in an organized and understandable fashion.
Customer oriented approach with a demonstrated concern and desire to work with and assist customers.
Good organizational skills with the ability to multitask, prioritize, and track many activities.
Outstanding oral and written communication skills.

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