AMS Verification Engineer Coventine Digital

5.0 - 10.0 years

6 - 15 Lacs

Pune, Bengaluru

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Key Responsibilities: Develop AMS verification environments from the ground up using SystemVerilog/UVM Own and execute test planning, AMS setup, and mixed-signal simulation Work on SerDes verification involving high-speed protocols (PCIe, USB 3.0, MIPI, etc.) Model and verify analog/mixed-signal blocks using wreal , RNM , and Verilog-A Perform simulations using VCS Primesim AMS and Primesim XA tools Collaborate closely with analog, digital, and system teams for integrated AMS verification

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Ams Verification Engineer Intverse It Solutions

4.0 - 8.0 years

15 - 20 Lacs

Bengaluru

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Key Responsibilities Architect and implement System Verilog/UVM-based testbenches and verification environments for analogmixed signal blocks and SoCs. Develop VerilogA , RealNumber Models (RNM) , WREAL models, and support cosimulation with SPICE for behavioral accuracy. Execute verification of highspeed serial protocols including PCIe , USB 3 , MIPI CSI/DSI , using constrainedrandom stimulus, assertions, monitors, functional coverage. Utilize tools like PrimeSim XA (VCS AMS) to run mixed-signal regressions and VerilogA analog simulations. Collaborate closely with digital, analog, synthesis, timing, and silicon bring-up teams to ensure spec traceability, debug failures, and validate first-pass silicon performance. Write thorough verification plans , track coverage closure, debug RTL/AMS models, document results, and drive continuous improvement of methodologies. Qualifications & Skills Bachelors/Masters in Electronics/Telecommunication, Computers, Electrical . 5+ years of mixed-signal/AMS verification experience; SoC-level IP/subsystem/SoC verification preferred. Deep proficiency in System Verilog , UVM , assertions, functional coverage, OOP testbench design. Strong expertise in VerilogA , RNM/WREAL , and building analog behavioral models Simply. Hands-on experience with PrimeSim XA/VCS AMS , Cadence Spectre/Xcelium, Synopsys AMS toolchains.

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Ams Verification Engineer Exiger Technologies

3.0 - 6.0 years

16 - 20 Lacs

Bengaluru

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Job Description: We are looking for a highly motivated Mixed-Signal Design Verification Engineer with 3+ years of experience in analog/mixed-signal verification. The ideal candidate should possess strong fundamentals in analog and digital design processes, along with hands-on experience in mixed-signal modeling and testbench setup. Responsibilities: Develop and maintain mixed-signal testbenches from scratch Write and manage Analog Mixed Signal models using VerilogAMS and real number modeling Debug mixed-signal simulations and analyze waveform results Utilize Synopsys tools (CustomSim/Primesim XA, Waveview) and Cadence Spectre environment Automate workflows using Unix shell scripting and Python Desired Skills: Strong knowledge of analog building blocks and top-level integration Expertise in mixed-signal simulation performance optimization Proficient in Unix/Linux environments Strong scripting and automation capabilities Excellent communication and problem-solving skills

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Ams Verification Engineer Intverse It Solutions

4.0 - 8.0 years

14 - 24 Lacs

Bengaluru

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Roles and Responsibilities Design verification using System Verilog, UVM, and SV/UVM methodologies. Experience with PrimeSim XA, WREAL, RNM, Verilog-A, and MIPI protocols. Proficiency in PCIe and USB 3 interfaces. Strong understanding of digital logic design principles and SoC architecture. Excellent problem-solving skills with attention to detail.

Posted 1 month ago

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