PE and LB timing Professional

2 - 3 years

4 - 5 Lacs

Posted:5 days ago| Platform: Naukri logo

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Job Description

Roles and Responsibility
Skill Job Description Open position Count
.LIB timing file generation Experience Level - 2-3 years 1
Need resource with the following skills:
.LIB timing file generation
Verilog Modelling
Analog design characterization - familiarity with Cadens spectre and Synopys Hspice
Additional help with Analog Quality Checks :
o EM/IR simulation
Please find the below mentioned JD for the replacement hiring.
1. Embedded product knowledge like UFS and eMMC
2. Embedded c , c++ & python knowledge is must
3. Automation background is also major priority
4. Experience on debugging using T32 or any tools
Experience : Within 5 Years.

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