Posted:3 days ago|
Platform:
On-site
Full Time
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's CSoC DV, resulting in no bugs in the final design.
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Minimum 8+ years of experience in ASIC Design Verification
Must have excellent knowledge of ASIC Design Flow and SOC architecture
Experience in developing complex testbench/model in verilog, System verilog or SystemC
Experience with coverage-based verification methodology
Experience in writing testplans and testcases
Excellent debug skills in functional simulations are must.
Experience in random test generation, coverage analysis, failure debug
Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have
Strong Verilog, SystemVerilog, PLI interface, C/C++, Python/Perl/shell scripts programming skills.
Must have good communication skills and the ability/desire to foster a team environment.
AMD
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