26 Hbm Jobs

Must know how and experience of different types of CNC machines like HMC, VMC, turning center, VTL, Horizontal Boring Machine, Vertical Turning Center and Turn-mills. Hands-on experience of Heavy parts Machining

Must know how and experience of different types of CNC machines like HMC, VMC, turning center, VTL, Horizontal Boring Machine, Vertical Turning Center and Turn-mills. Hands-on experience of Heavy parts Machining

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

designations : Deburring technicians experiences : 1 to 10 yrs salary : 15 k to 35 k locations : Chennai -Irungattukottai job descriptions : have experiences in HBM , VTL ,Deburring technicians contact us or WhatsApp 7550079132

Good setting and programming knowledge in VMC,HMC & HBM Makino & Doosan machine Well experience knowledge in programming Benefits : Accommodation free of cost ,Food 50% subsidy For 3 Times, Double OT, Esi,Pf,Bonus,Gratuity,Etc. PMAC.PVT.LTD Email id: hr@pmacindia.com Role & responsibilities

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR). Experience in silicon bringup, functional validation, characterizing, and qualification. Experience with board schematics, layout, and debug methodologies with using lab equipment. Preferred qualifications: Experience in hardware emulation with hardware/software integration. Experience in coding (e.g., Python) for automation development. Experience in Register-Transfer Level (RTL) design, verification or emulation. Knowledge of SoC architecture including boot flows. Knowledge of HBM/DDR standards. Responsibilities Develop and execute tests for memory controller High Bandwidth Memory (HBM) post-silicon validation and on hardware emulators and assist in bring-up processes from prototyping through post-silicon validation. Drive debugging and investigation efforts to root-cause, cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bringup and production. Ensure validation provides necessary functional coverage for skilled design. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.

Build your career with Sykatiya Technologies! Sykatiya Technologies values both technical ability and the attitude of its highly talented team, which is evident in their contributions to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, as well as experience in FINFET technology and the 32G-112G range of SERDES. The successful candidate should have taken at least one block from circuit design to layout closure and be capable of guiding the layout team for high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, etc., is essential. The candidate should be able to work independently, mentor juniors, and have exposure to post-silicon validation. If you are a motivated Analog Design Engineer looking to work with a team of experts and contribute to cutting-edge projects, we encourage you to apply and be a part of our innovative team at Sykatiya Technologies.,

Position Clarification Dr. Reddys Laboratories Ltd. Scientific Business Officer Position: Scientific Business Officer Incumbent: O1-1A Supervisor and Position (L+1): Regional Sales Manager Superior and Position (L+2): Sales Manager PURPOSE To generate prescription through science based communication within assigned territory by implementing defined strategies. Also ensure product availability at chemist stores to prevent Rx substitution. OPERATING NETWORK The role holder works in active collaboration with PMT ,Distribution and services the following customers Doctors, Stockists, Chemists ,Purchase Officers in hospitals . MINIMUM REQUIREMENTS Required Education: Science Graduate/ B Pharm. MBA will be desirable. Minimum Experience Minimum 2.5 Years Experience in niche therapies Knowledge: What Knowledge is required? How will it be used?Basic AnatomyTo understand science related to our productsBasics of Marketing & SalesTo understand the marketing strategy and appreciate the brand communication prepared by MarketingComputer Knowledge (MS Office, Internet)To use various IT Applications (Palm, MS Office etc) in day to day operations of field sales.Product KnowledgeOf the assigned therapy to have a confident communication with the doctors. Key Skills Required: Particulars1Communication In chamber communication. Positive body language in front of the customers.2Influencing selling the perception created by the PMT to the doctors. Convincing the chemist/ stockist to keep the stocks.3High Energy Level to cover his/ her territory and achieve targets of coverage of all levels of customers. i.e. doctors, stockist, chemist etc4Learnability to inculcate the product knowledge and marketing strategy related to products every quarter and quickly convert it to Rx in the doctors chamber.5Decision Making CRM Investments decisions to be taken..6Comprehensions to comprehend articles/ journals related to molecules and engage the doctor in a dialogue.7Perseverance To face the high rate of rejections associated with this job and keeps the spirits high.8Analytical Skills to analyze the performance. ROLE Responsibilities: Particulars Personally Do / Ensure Weightage (%)Frequency 1Sales Target Achievement - In order to achieve growth and profitability in a given territory - Monthly Planning and ensuring coverage of all the doctors to implement the designed strategies for the area assigned by meeting core as well as non core doctors in the assigned territory as per the list. Doctor Calls / chemist visits to determine right frequency of visits to core and non-core doctors. Sampling plan - RCPA to analyze movement of products/ competitor products to understand the Rx trend of our products/ doctor potential Ensures Stock Availability in case of the requirement POB to be done Inform chemist post call about the doctor communication an influence to keep stocks to avoid substitution. Prepare Doctor Product Matrix out of the data received by RCPA - In Chamber Communication Based on the doctor product matrix, call objective, RCPA Finding etc position the call to achieve the objectives. Carry out the communication in the chamber in a dialogue mode by discussing literatures as well as probing the doctor. Demand specific prescription support from the doctor. - Implements all PMT Designed activities / strategies to improve brand recall and increase prescription - Provide solutions to any doctor queries with help of Line Manager and PMTDO 60 2Compliance to field processes - Follow all the field processes as defined in the SOPs with respect to - Doctor Coverage Core / Non core - RCPA - Stockists & Chemist coverage - Sync of daily call reports - Expense Statements - STP & SFC - Updates customer list as and when required - Visit stockist to collect secondary statements to track secondary progress DO 20 3CRM and Business Development - In order to build customer and market base for achieving present and future business objectives - Understand the psyche of the doctor and ensure communication accordingly; Keep track of specific customer needs and provide feedback regarding the same to Line Manager / HO - Device innovative approaches and strategies to build strong relationships with doctors. - Propose and discuss investment areas with RSM and take necessary approval to analyse and commit on return on Investment - Conduct initiatives line CMEs/ Patient Awareness Camps/ Doc Association meetings/ etc - Analyze doctor's behavior and combat unfavorable behaviors (like disinterest, favoring competitors etc) by adopting the right strategy - Identify potential for new business in the territory by spotting opportunities like a new doctor, a new hospital etc. - Study competition critically to understand opportunities and evaluate self performance critically by building local tactics DO 20 On going

SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Description: The verification team is looking for a Senior Design Verification Engineer to contribute on the verification of Network on Chip IPs, Subsystems having adequate knowledgeble on the boot flow. The individual will help architect, develop and use simulation and/or formal based verification environments, at block, subystem , Fulchip level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs. Responsibilities: Plan verification of complex digital design blocks by fully understanding the architecture and design specification Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics General requirements: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification Strong understanding of different phases of ASIC and/or full custom chip development is required Experience in block level NOC (Network on Chip) verification is a plus Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus Special Requirements : Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog; Test plan development and test writing; Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip; Functional coverage writing, coverage collection and analysis, coverage closure; Writing System Verilog assertions and assertion based verification; and, Running regressions, automation using scripting languages such as PERL and verification closure Education Requirements: Masters / B.Tech / M.Tech Years of Experience : 5+ Years #LI-SG

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,

As an Analog Design Engineer at Sykatiya Technologies, you will be an integral part of our highly talented team that focuses on Technical Ability and a positive Attitude. Your contributions to projects will reflect our commitment to excellence for our customers. Our team consists of skilled engineers and experts in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, along with experience in FINFET technology and the 32G-112G range of SERDES. In this role, you will be responsible for taking at least one block from circuit design to layout closure. You should also be able to guide the layout team in high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, and being able to work independently while mentoring junior team members are essential qualities we are looking for. If you have exposure to post-silicon validation, it would be considered a plus. Join us at Sykatiya Technologies and be part of a dynamic team that values technical expertise, a positive attitude, and a commitment to excellence in Analog Design.,

3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Deliver No.Performance ParameterMeasure1.Product design, engineering and implementationCSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards2.Capability development% trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) Applications from people with disabilities are explicitly welcome.

Role & responsibilities Test bench development and debug UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based testing. Coverage analysis (code, functional, assertion) Verification plan reviews, Verification reviews Back-annotated netlist simulation execution and debug Debug failing cases & Coverage improvements.

designations : HBM Operator experiences : 2 to 15 years salary : 20 k to 35 k locations :Chennai job descriptions : candidates should have experiences in HBM or VTL or deburring technician interested please contact or WhatsApp7550079132

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Long Description 4. Analog Circuit Design : Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Experience - 7+ Yrs + Lead/Architect Location - Bangalore 5. DFT - ATPG, MBIST Location - Bangalore, Kochi, Pune, Hyderabad Experience - 7 years + DFT Lead Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Skillset: DV | System Verilog | UVM | Protocol Expertise Must-Have Skills: Strong expertise in System Verilog (SV) and UVM Proven experience in Test Bench Development Deep protocol knowledge in at least one of the following: PCIe / UCIe / CXL / NVM AXI / ACE / CHI Ethernet / RoCE / RDMA DDR / LPDDR / HBM Key Responsibilities : Lead and drive verification for block, subsystem, or SoC level designs Strong experience in IP/subsystem/SoC verification using SV/UVM Verification experience with ARM or RISC-V CPU based subsystems Work with C/Assembly for low-level testing Perform Power Aware Simulations using UPF Location : Bangalore | Hyderabad | Cochin | Pune

Role & responsibilities Knowledge of Machine Maintenance like press machine, VMC and HMC, VTL, HBM. Key Responsibilities 1. Able to attend to all electrical-related works, cable routing, and machine commissioning. 2. Should be able to handle the breakdowns with the team and individually. 3. Should have 11 kVA or 33 kVA electrical lenience. 4. Liaison with TSPDCL. 5. Awareness of motors, PLC, HMI, ladder drawings, electrical circuits and related works. 6. Awareness of EMS, QMS, and OSHAS Documentation. 7. Awareness on 5S Implementation and Guidance to Supervisor and below. 8. Able to complete the preventive maintenance according to the schedule. 9. Awareness of Safety Precautions while working on electrical works. 10. Should follow up on the logbook records, like DG set diesel consumption, electrical records, daily work details, and spare usage. 11. Knowledge in mechanical-related breakdowns. 12. Should have leadership qualities to lead the team and manage the works. 13. Should have analysis skills to break down the root cause. 14. Should be aware of the criticalness of machinery. 15. Awareness of electrical power distribution-related equipment like DG, transformers, and breakers. 16. Knowledge in identification of cable sizes and electrical spares. 17. Should have to share the knowledge of work with technicians and below workers. 18. Should be implementing Kaizen and horizontal deployment. Qualifications, Experience Experience: 13 to 18 years Education: Diploma/ B Tech (Electrical Preferred candidate profile

Role & responsibilities • Knowledge of Machine Maintenance like press machine, VMC and HMC, VTL, HBM Key Responsibilities 1. Able to attend to all mechanical-related work. 2. Should be able to handle the breakdowns with the team and individually. 3. Awareness on 5S Implementation and Guidance to Supervisor and below. 4. Able to plan and implement preventive maintenance according to the schedule. 5. Should have good knowledge of pneumatic and hydraulic circuits. 6. Should have decision-making skills. 7. Liaison with other departments. 8. Awareness of fasteners, weld joints, and pipeline routing. 9. Awareness of electrical-related works. 10. Should have leadership qualities to support below-level workmen. 11. Should have a good relationship with other departments. 12. Should have good knowledge in documentation guidance for QMS, EMS, and OSHAS. 13. Awareness of safety precautions while working on mechanical works. 14. Should follow up on the logbook records, like oil consumption, daily work details, and spare usage. 15. Should have leadership qualities to lead the team and manage the work. 16. Able to identify the bearings, seals, belts, bolts and mechanical spares. 17. Knowledge in breakdown in utilities. 18. Should be aware of the criticalness of machinery. 19. Should have to share the knowledge of work with technicians and below workers. 20. Knowledge of the root cause analysis, why-why analysis. 21. Should be implementing Kaizen and horizontal deployment. Qualifications, Experience Experience: 13 to 18 years Education: Diploma/ B Tech (Mechanical) Preferred candidate profile

Job responsibilities: (edit as per the requirement) Leads projects with high resource, risk and/or complexity Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity Continually evaluates technology effectiveness/data interoperability of complex systems Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products Communicates highly-complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view. Experience and Technical Skills required (edit as per the requirement): At least 4+ to 8 years of experience with Verification and Design Working knowledge with Memory Models like DDR, HBM, LPDDR protocols is a must Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results. Excellent problem-solving and debugging skills Qualifications BE/BTech/ME/MS/MTech in Electrical, Electronics Comm or Computer Science Engineering Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity

Leads projects with high resource, risk and/or complexity Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity Continually evaluates technology effectiveness/data interoperability of complex systems Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products Communicates highly-complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view. Experience and Technical Skills required (edit as per the requirement): At least 7+ to 12 years of experience with Verification and Design Working knowledge with Memory Models like DDR, HBM, LPDDR protocols is a must Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results. Excellent problem-solving and debugging skills Qualifications BE/BTech/ME/MS/MTech in Electrical, Electronics Comm or Computer Science Engineering Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity

Horizontal boring machine operator(HBM) Knowledge of CNC programming((Heidenheim/Fanuc Controller) Detailed knowledge of fixtures, toolings etc. Must have knowledge of cutting parameters, geometric symbols. Able to study drawings, blue prints. should able to do job settings, finish job inspection individually. Working in all three shifts ITI NCVT certification is mandatory. Minimum 3 years of experience as HBM machine operator. Experience in heavy machine industry will be an added advantage

Good operating and setting knowledge in VMC,HMC & HBM Makino & Doosan machine Benefits : Accommodation free of cost ,Food 50% subsidy For 3 Times, Double OT, Esi,Pf,Bonus,Gratuity,Etc. PMAC.PVT.LTD Contact : HR - 9566947765 , hr@pmacindia.com Role & responsibilities

Hi All, We are hiring for MNC company Randstad India Pvt Ltd ( Bangalore Peenya Location ) We are looking for ITI & Diploma ( Mechanical & tool & Die Making ). Gender - Male, Education - ITI & Diploma ( Mechanical & tool & Die Making ). Experience - 1 to 10 Years Salary: 15% to 20% Hike based on Interview ). Benefits: PF, ESIC, & Transport, Shift Timings: 8 Hours work ( Rotational shifts ) 6 days working (Monday Saturday) Interview Mode - Face to Face interview. Job Profile: We have openings for CNC, VMC, VMC Double Column Operator, VMC Programmer, CNC Turning operator, CNC VTL Incharge - with programming capability, CNC VTL Operator. EDM & Wire Cut Operator Venkateswarlu K 9676590526 venkateswarlu.k@randstad.in

Senior Analog Manager /Manager /Lead ( HBM / IO ) www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Sevya is an innovative semiconductor design company dedicated to pushing the boundaries of technology. We focus on developing cutting-edge solutions that empower the electronics industry. Our mission is to drive the future of technology, and we are seeking talented individuals to join our dynamic team. Job Description: Sevya is architecting and designing a HBM transceiver in advanced FinFET node. Sevya needs analog designers at all levels with skills in the areas of analog circuit design, custom digital design for SerDes and other high speed IP applications, signal and power integrity modeling, pre and post silicon debug. Familiarity with HBM, DDR and other memory standards in highly desirable but not necessary if the candidate has good knowledge of high speed design. Candidates with experience of linear circuits such as high bandwidth LDOs, amplifiers, charge pumps etc. who want to explore high speed design are also welcome, we have appropriate work and there will be opportunities to learn more. Specifically we are looking for people with approximately 10-15 yrs of experience for Senior mnager positions and 7-10 yrs for lead positions. Candidates with higher experience also welcome for appropriate role. Responsibilities: I/O Architecture Design: Develop and design the input/output architecture for integrated circuits using HBM technology. Signal Integrity Analysis: Perform signal integrity analysis to ensure reliable and high-speed data transfer between the HBM memory and the rest of the system. Circuit Design: Design and optimize circuits for HBM I/O interfaces, considering factors such as power consumption, area, and performance. Collaboration: Work closely with cross-functional teams, including system architects, memory designers, and layout engineers, to ensure seamless integration of HBM I/O interfaces into the overall system. Standards Compliance: Ensure that HBM I/O designs comply with industry standards and specifications, such as JEDEC standards for high-bandwidth memory. Simulation and Modeling: Utilize simulation tools and models to validate the design's performance and address any potential issues related to signal integrity, power delivery, and thermal considerations. Debugging and Troubleshooting: Identify and resolve issues during the testing and debugging phases of the design process. Documentation: Prepare detailed documentation of the HBM I/O design, including specifications, test plans, and design guidelines. Requirements: Bachelor's degree or higher in Electrical Engineering or a related field. A minimum of 7-15 years of experience in analog circuit design within the semiconductor industry. Proven expertise in designing analog blocks, including Bandgap references, PLLs, LDOs, and High-Speed I/O circuits. Proficiency in industry-standard Electronic Design Automation (EDA) tools for analog design and simulation. Strong knowledge of semiconductor fabrication processes and technologies. Exceptional problem-solving and analytical skills. Effective communication and teamwork abilities. Preferred Qualifications: - Experience in mixed-signal circuit design. - Familiarity with high-speed data communication interfaces. - Knowledge of low-power design techniques. - Published research or patents related to analog design. Why Join Us: Sevya is committed to creating an environment of innovation, professional growth, and collaboration. As an I/O Design Engineer, you will be a part of groundbreaking projects and a team that values creativity and excellence. We offer competitive compensation, benefits, and the opportunity to be a driving force in the future of semiconductor technology. If you are an ambitious Analog Design Engineer eager to push the boundaries of analog design and help shape the future of technology, we encourage you to apply. Join us in our mission to redefine what's possible in the world of electronics! Skills: Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior Analog Manager /Manager /Lead ( HBM / IO ) www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Sevya is an innovative semiconductor design company dedicated to pushing the boundaries of technology. We focus on developing cutting-edge solutions that empower the electronics industry. Our mission is to drive the future of technology, and we are seeking talented individuals to join our dynamic team. Job Description: Sevya is architecting and designing a HBM transceiver in advanced FinFET node. Sevya needs analog designers at all levels with skills in the areas of analog circuit design, custom digital design for SerDes and other high speed IP applications, signal and power integrity modeling, pre and post silicon debug. Familiarity with HBM, DDR and other memory standards in highly desirable but not necessary if the candidate has good knowledge of high speed design. Candidates with experience of linear circuits such as high bandwidth LDOs, amplifiers, charge pumps etc. who want to explore high speed design are also welcome, we have appropriate work and there will be opportunities to learn more. Specifically we are looking for people with approximately 10-15 yrs of experience for Senior mnager positions and 7-10 yrs for lead positions. Candidates with higher experience also welcome for appropriate role. Responsibilities: I/O Architecture Design: Develop and design the input/output architecture for integrated circuits using HBM technology. Signal Integrity Analysis: Perform signal integrity analysis to ensure reliable and high-speed data transfer between the HBM memory and the rest of the system. Circuit Design: Design and optimize circuits for HBM I/O interfaces, considering factors such as power consumption, area, and performance. Collaboration: Work closely with cross-functional teams, including system architects, memory designers, and layout engineers, to ensure seamless integration of HBM I/O interfaces into the overall system. Standards Compliance: Ensure that HBM I/O designs comply with industry standards and specifications, such as JEDEC standards for high-bandwidth memory. Simulation and Modeling: Utilize simulation tools and models to validate the design's performance and address any potential issues related to signal integrity, power delivery, and thermal considerations. Debugging and Troubleshooting: Identify and resolve issues during the testing and debugging phases of the design process. Documentation: Prepare detailed documentation of the HBM I/O design, including specifications, test plans, and design guidelines. Requirements: Bachelor's degree or higher in Electrical Engineering or a related field. A minimum of 7-15 years of experience in analog circuit design within the semiconductor industry. Proven expertise in designing analog blocks, including Bandgap references, PLLs, LDOs, and High-Speed I/O circuits. Proficiency in industry-standard Electronic Design Automation (EDA) tools for analog design and simulation. Strong knowledge of semiconductor fabrication processes and technologies. Exceptional problem-solving and analytical skills. Effective communication and teamwork abilities. Preferred Qualifications: - Experience in mixed-signal circuit design. - Familiarity with high-speed data communication interfaces. - Knowledge of low-power design techniques. - Published research or patents related to analog design. Why Join Us: Sevya is committed to creating an environment of innovation, professional growth, and collaboration. As an I/O Design Engineer, you will be a part of groundbreaking projects and a team that values creativity and excellence. We offer competitive compensation, benefits, and the opportunity to be a driving force in the future of semiconductor technology. If you are an ambitious Analog Design Engineer eager to push the boundaries of analog design and help shape the future of technology, we encourage you to apply. Join us in our mission to redefine what's possible in the world of electronics! Skills: Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"