4 Erc Jobs

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 310 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

Role & responsibilities Respond to customer HR inquiries through multiple channels - Phone, chat and web tickets.(calls, webforms, emails, chats and voicemails). Develop an understanding of US Human Capital Management (HCM) nuances, including payroll, benefits, talent, policies etc. Gain hands-on experience with applications like Workday, Oracle, SAP, and UKG. Developing a higher level of accuracy and speed in task completion, demonstrating the ability to efficiently process transactions, showing proficiency in client service Communicate (verbal and written) with customers from different countries and cultures. Utilize the client knowledge base to find answers and solutions independently Own incidents/issues end to end with minimum guidance. Understanding and adherence to contractual goals and Service Level Agreements (SLAs) Document recurring and known service request resolutions in the knowledge base. Demonstrate flexibility in working in different shifts (24x7 operations). Developing a high level of accuracy and speed in task completion, demonstrating the ability to efficiently close tickets, showing proficiency in client service

Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in PnR tools like ICC/Innovus with regards to physical convergence must. Good understanding of PD flows and overall backend tool flow would be beneficial. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and DRV. TCL/PERL Scripting is plus. Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable. Interested candidates can share their resumes to shubhanshi@incise.in

Analog layout design requires knowledge of designing layouts of complex VLSI (very large scale integration) circuits using graphic editing tools in the Analog domain. A major portion of the job is in the creation of new physical design data from concepts, partial schematics, or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Your Role and Responsibilities Hands-on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below , and also take leadership roles in delivery of IPs. Work on Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimizations . Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. Participate in building and enhancing layout flow for faster, higher quality design process. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks. Collaborate with Circuit Designers to solve challenging problems. Writing SKILL/PYTHON scripts to automate repetitive tasks. Work with Place and Route engineer to integrate custom macros into the top level. Able to perform design reviews across global teams. Work closely with required global teams to ensure the success of the whole product. Leadership in delivery of macros we plan to own from India. Job Requirements Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers , etc. Experience in designing layouts for high-speed circuits is a plus. Layout experience in the following technology nodes: 3nm, 5nm, and 7nm FinFET . Good team worker with multi-discipline, multi-cultural, and multi-site environments. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability, and failure mechanisms. Good problem-solving skills are essential where problems are analyzed upfront, identifying gaps, and providing optimum solutions. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required Education Bachelor's Degree Preferred Education Master's Degree Required Technical and Professional Expertise The Analog layout design engineer with experience in next-generation Ultra high-speed serial IO link (HSS) interface for Cognitive, ML, DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high-speed 32G/50G/112G IO link interfaces . Preferred Technical and Professional Experience Experience in 7 and 14 nm analog layout design . Working on Cutting edge technology and HSS domain. Quick learner, deep layout design knowledge, problem-solving skills, and good communication skills with cross teams across the Geos.