4 Dft Methodologies Jobs

As a DFT Engineer at Google, you will play a key role in developing custom silicon solutions for Google's direct-to-consumer products. Your expertise in DFT methodologies and Electronic Design Automation (EDA) tools like Tessent will contribute to the innovation and performance of products used by millions worldwide. Working closely with RTL and Physical Designer Engineers, you will help shape the next generation of hardware experiences. Your responsibilities will include working on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage and power domains. You will also be involved in writing basic scripts to automate the DFT flow and developing tests for production in the Automatic Test Equipment (ATE) flow. To be successful in this role, you should have a Bachelor's degree in Electrical or Electronics Engineering, along with at least 3 years of experience in DFT methodologies. Experience in areas such as ATPG, Low Power designs, BIST, JTAG, and IJTAG tools and flow will be beneficial. Preferred qualifications include experience in architecting/developing DFT flows and methodologies, as well as collaborating with Design, Physical Design (PD), and Static Timing Analysis (STA) teams. Strong scripting skills in languages like Python and TCL are also desired. Join us in our mission to organize the world's information and create helpful experiences for users through innovative hardware technologies. Your contributions will play a vital role in making people's lives better through technology.,

As an engineer of NVIDIA's Software Quality Assurance (QA) team, you will play a crucial role in orchestrating the Software Quality processes for CAD tools and flows that support all semiconductor products. You will be working on infrastructure and software used to test complex semiconductor devices, including developing in-house tools for Design for Test (DFT) using languages like C++, Python, and TCL. This role requires a diverse skill set and a willingness to tackle challenges head-on. Your responsibilities will include providing support for testing and validation processes, architecting automated and customizable Software Quality processes, crafting test plans and cases, automation of testing, maintaining regression testing frameworks, performing code reviews and testing, and ensuring the delivery of high-quality, bug-free software applications. You will collaborate closely with team members to provide DFT and DFP methodologies for cutting-edge chip designs and support the development of tools using C++, Python, and TCL. To be successful in this role, you should have a BS or MS in Electrical Engineering, Computer Science, or Computer Engineering with a minimum of 4 years of experience in a Software QA role. You should possess knowledge of various software testing techniques, code reviews, testing tools such as TestRail or Zephyr, CI/CD tools like Jenkins and GitLab, and have skills in Python, TCL, or C++. Experience with defect tracking tools like JIRA and lab software and hardware support is also essential. To stand out, additional knowledge or experience with DFT, BDD processes, Verilog, ASIC design principles, and logic cells will be advantageous. NVIDIA is known for being one of the most desirable employers in the technology industry, attracting forward-thinking and talented individuals. If you are a creative and autonomous professional looking to make an impact, we encourage you to apply and join our diverse team today.,

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. 4. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. 5. Debug and resolve test-related issues in simulation, silicon validation, and production. 6. Work closely with the physical design team to implement scan and clock constraints for timing closure. 7. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. 8. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 2-10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including scan insertion, BIST, and ATPG. 3. Experience with EDA tools such as Synopsys Tetramax/DFTMax, Cadence Modus, or Mentor Tessent. Proficiency in 4. Verilog/SystemVerilog and scripting languages (Python, TCL, Perl). 5. Solid understanding of STA concepts and constraints related to DFT. 6. Experience in debugging silicon and ATE test patterns. Knowledge of test standards like IEEE 1149.x (JTAG) and 1500. 7. Excellent problem-solving skills and ability to work in a collaborative environment. Preferred Qualifications: 1. Experience with low-power DFT techniques. 2. Familiarity with fault diagnosis and yield improvement methodologies. 3. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. 4. Knowledge of machine learning or AI techniques for test optimization. 5. Hands-on experience with multi-core and hierarchical DFT architectures. Why Join Us? 1. Be part of a team driving innovation in the semiconductor industry. 2. Work on challenging and impactful projects in a supportive environment. 3. Opportunities for career advancement and skill development. 4. Competitive salary and comprehensive benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams. Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. Debug and resolve test-related issues in simulation, silicon validation, and production. Work closely with the physical design team to implement scan and clock constraints for timing closure. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including ATPG/MBIST/Scan Insertion Verilog/ System Verilog and scripting languages (Python, TCL, Perl). Solid understanding of STA concepts and constraints related to DFT. Experience in debugging silicon and ATE test patterns. Excellent problem-solving skills and ability to work in a collaborative environment. Familiarity with fault diagnosis and yield improvement methodologies. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. Knowledge of machine learning or AI techniques for test optimization.